Static Timing Analysis Patents: Leaders & Filing Trends 2026
Filing growth compares 2021 (45 records) with 2024 (27) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,552 records in scope (CR5), not by the ranked leaders only.
What the static timing analysis patent record shows
Static timing analysis (STA) sits at the core of digital chip verification: it checks that signal paths meet setup and hold requirements without running a full transistor-level simulation. The patent record for this topic spans 1,552 published records from 2015 through the 2026 cut-off, drawn from filings that reference static timing analysis or evaluation directly in their claims. Because STA is a verification method rather than a physical structure, most of the record clusters inside digital data processing classifications rather than device or materials classes.
The assignee ranking is dominated by a mix of EDA tool vendors, foundries and large semiconductor manufacturers rather than pure-play startups, which is consistent with STA being a method embedded deep inside existing design flows. The filing trend and technology composition below give a view of where that claim space is concentrated and where it has thinned out.
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Filing trends and technology composition
Two views of the same 1,552-record dataset: how filing activity has moved year over year, and which IPC subclasses the claims fall into.
Filings peaked in 2017, pulled back through the early 2020s
Annual filings ran as high as 51 in 2017. Using only complete years, the trend moved from 45 filings in 2021 down to 27 in 2024 — a 40% decline over that span. Counts for 2025 and 2026 will keep rising as later publications catch up, since publication typically lags filing by around 18 months.
G06F dominates; everything else is a minority share
G06F (electric digital data processing) appears in 93.2% of the 1,552 records, confirming that STA patent activity is overwhelmingly claimed as a computational method. G01R (measurement) and H01L (semiconductor devices) follow at 7.9% and 6.4% respectively, with H03K, H10D, H04L, G06Q and G11C each under 3% — these smaller classes mark where STA claims touch adjacent hardware, memory or communications domains rather than pure computation.
Shares are the percentage of the 1,552 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on EDA & Chip Design: Static Timing Analysis Patent Landscape with Eureka
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US20240037306A1 — Static timing analysis method and static timing analysis system
Filed by Realtek, this application describes a method that maps a standard cell library to find target sequential cells, runs a logic test to identify pin combinations with a mutual non-controllable relationship, and removes the timing constraints tied to those pin combinations as redundant — reducing the constraint set an STA run has to check.Abstract text condensed from the original filing.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20090024974A1 | Method and program for designing semiconductor integrated circuit | 328 |
| 2 | US7487475B1 | Systems, methods, and apparatus to perform statistical static timing analysis | 299 |
| 3 | US6405348B1 | Deep sub-micron static timing analysis in the presence of crosstalk | 277 |
| 4 | US7093208B2 | Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space w… | 234 |
| 5 | US7149999B2 | Method for correcting a mask design layout | 233 |
| 6 | US7454731B2 | Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques | 221 |
| 7 | US8336010B1 | Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits | 206 |
| 8 | US7890915B2 | Statistical delay and noise calculation considering cell and interconnect variations | 194 |
| 9 | US7590953B2 | Static timing analysis and dynamic simulation for custom and ASIC designs | 194 |
| 10 | US4924430A | Static timing analysis of semiconductor digital circuits | 180 |
Citation counts favour older filings simply because they have had longer to accumulate citations inside this corpus — treat them as a signal of influence on the field, not as a ranking of current relevance.
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Browse MCP servers →What the numbers mean for a filing decision
Four read-outs from the dataset that matter more than the raw counts on their own.
The top of the field is crowded
Five assignees hold 41.0% of all 1,552 records in scope, and the top ten extend that to 54.3%. New entrants filing broad STA method claims are filing into space that large EDA vendors, foundries and IDMs have already claimed heavily.
A real pullback, not noise
Filing activity fell 40% from 45 in 2021 to 27 in 2024, using only years that are complete enough to compare. That is a meaningful contraction in new STA filing activity rather than a plateau, though later years will still revise upward as publications catch up.
Claims sit almost entirely in software methods
G06F carries 93.2% of the 1,552 records, dwarfing every other class. G01R (measurement), H01L (semiconductor devices) and the remaining classes each sit under 8%, showing that STA patent activity is concentrated on computational method claims rather than measurement hardware or device structure.
US filing office leads by a wide margin
The United States receives far more STA filings than any other office, with China, Japan, WIPO/PCT, Europe and Taiwan trailing well behind. That skew reflects where EDA and large-chip design activity is concentrated rather than where manufacturing happens.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to eda & chip design: static timing analysis patent landscape, with the prior art for and against each one.
Where to take this analysis
The dataset points to a few concrete next steps depending on what you are trying to decide.
Check freedom to operate against the leaders
With 41.0% of records held by five assignees, any new STA method claim should be checked against their filings before drafting, especially around constraint-reduction and statistical timing techniques.
Explore assignee filings in Eureka →Watch the smaller IPC branches for open space
Classes like G11C, G06Q and H04L each hold under 1% of records, suggesting STA claims touching memory, business-process integration or data transmission are comparatively under-claimed.
Map white space in Eureka →Track the post-2021 filing pullback
The 40% drop from 2021 to 2024 is worth monitoring as 2025-2026 data fills in, to see whether it reflects consolidation among top filers or a genuine slowdown in new STA method innovation.
Set up a filing trend alert in Eureka →Common questions about static timing analysis patents
The assignee ranking is led by a large diversified technology and semiconductor manufacturer, with EDA tool vendors and foundries filling out the rest of the top five. Together the top five assignees hold 41.0% of all 1,552 records in scope, and the top ten extend that to 54.3%. This means STA claim space at the top is concentrated among a small number of long-standing filers rather than spread evenly across the industry.
Filing activity peaked in 2017 at 51 filings and has trended down since. Comparing only complete years, filings fell 40% from 45 in 2021 to 27 in 2024. Later years in the dataset will revise upward as publication catches up with filing, since publication typically lags filing by around 18 months, but the multi-year direction through 2024 is a genuine decline rather than noise.
The overwhelming majority of records, 93.2% of the 1,552 in scope, fall under G06F, the classification for electric digital data processing, because STA is fundamentally a computational method. Smaller shares touch G01R (electric and magnetic measurement, 7.9%) and H01L (semiconductor devices, 6.4%), with even smaller slivers in classes like H03K, H10D, H04L, G06Q and G11C. A single record can carry multiple classes, so these percentages add up to more than 100%.
The United States receives by far the most filings in this dataset, at 1,151 records, well ahead of China at 80 and Japan at 79. WIPO/PCT filings sit at 69, followed by the European Patent Office at 55 and Taiwan at 43. This distribution tracks where major EDA vendors and large chip-design organisations are headquartered rather than where wafer fabrication capacity sits.
US20240037306A1, filed by Realtek and published in 2024, describes a static timing analysis method that maps a standard cell library, runs a logic test to find pin combinations with a mutual non-controllable relationship, and strips the timing constraints tied to those combinations as redundant. The practical effect is a smaller constraint set for an STA tool to evaluate on sequential cells built from a logic gate, selection circuit and register circuit. Anyone implementing a similar redundant-constraint-removal step in an STA flow should review this filing's exact claim scope before proceeding.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.