This landscape covers 799 published records filed or published between 2015 and the 2026-07-31 data cut-off, matched against a search string built around printed circuit delamination terminology. That figure counts patent families as recorded in the assignee ranking, which is the fairer unit than raw document counts because it removes double-counting from continuations and multi-jurisdiction filings of the same invention. The true current total is likely higher than 799, since publication typically lags filing by around eighteen months and the most recent one to two years of this dataset are still filling in.

The ranking covers 100 companies, with the leading filer holding 49 records, fifth place at 21 and tenth place at 15. The top 5 filers combined account for 21.3% of all 799 records in scope, and the top 10 combined account for 31.5%, so a majority of the field sits outside the leading group. That mix of a clear leader and a long tail of smaller filers means competitive monitoring needs to watch both the top names and new single-filing entrants.

Filing activity peaked at 44 records in 2019, the highest single year in this dataset, then eased before climbing again: 2021 to 2024 saw filings rise from 17 to 26, a 53% increase over that three-year span. The 2025 and 2026 figures in the raw trend look lower still, but that reflects the roughly 18-month lag between filing and publication rather than an actual slowdown, so those final years should not be read as declining activity.

H05K, the printed circuits and assemblies classification, touches 52.1% of the 799 records, and H01L, semiconductor devices, touches 21.0%, making board- and package-level claims the densest part of the field. B32B, layered products and laminates, sits at 13.1%, while the polymer chemistry classes C08L, C08J, C08K and C08G each account for 11.3% or less. Because a single record can carry more than one IPC classification, these shares add up to more than 100%, and they point to material-composition claims being comparatively less crowded than structural ones.

US20170194170A1, filed by Texas Instruments and published 2017-07-06, describes a method that applies a die attach material to a die pad, mounts an integrated circuit die to that pad through the die attach material, and then prints a separate adhesion deposition material specifically at the interface between the die and the pad to mitigate delamination. The claim is anchored at that interface rather than at the bulk composition of the die attach material itself. Anyone drafting a new die-attach delamination-mitigation method should check their approach against this interface-level claim before finalising a design.