ESD Protection Design Patents: Leaders, Trends & White Space 2026
- Filing has cooled since 2018. the peak year for new ESD protection filings, with the 2022 midpoint already down to 27 and no assignee showing latest-year momentum in the ranking.
- The US is the dominant filing venue. 775 records route through the United States, more than seven times the Chinese filing count of 76, which says a lot about where enforcement risk concentrates.
- Foundational clamp patents still carry the citation weight. the five most-cited records date to the 1990s and early 2000s, meaning core SCR and LVTSCR clamp topology is old, well-tested prior art rather than open ground.
Filing growth compares 2021 (33 records) with 2024 (26) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,278 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Electrostatic discharge protection design sits at the intersection of circuit topology and device physics: clamp circuits, silicon-controlled rectifiers, diode strings and guard structures built to survive a human body model or charged device model event without corrupting the core circuit they protect. This dataset pulls 1,278 patent families filed between 2017 and 2026 that specifically claim ESD clamp design, capacitance loading trade-offs, or latch-up immunity under IPC classes covering semiconductor devices and protective circuit arrangements.
Because publication trails filing by roughly eighteen months, the 2025 and 2026 counts in any trend chart understate real filing activity; treat the last one to two years as a floor, not a ceiling.
Filing trend and technology composition
Two views of the same 1,278 families: how filing has moved year over year, and which IPC subclasses carry the claim volume.
A declining filing curve
Annual filings ran from 44 in 2017 to a peak of 47 in 2018, then eroded to 27 by the 2022 midpoint and toward zero in the most recent, still-incomplete year. That shape reads as a maturing field rather than a growing one: the core clamp and trigger topologies were largely staked out in the 1990s and 2000s, and recent filing activity is topping up rather than expanding the claim space.
Concentration in two subclasses
H01L (semiconductor devices) accounts for 960 of the records and H02H (protective circuit arrangements) for 563, together dwarfing the next tier of H10D and H10W at 254 each. H03K (pulse technique and logic), H10N, H05F and H03F trail well behind, which marks them as the thinner, less-contested branches of this landscape rather than dead ends.
Shares are the percentage of the 1,278 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Electrostatic Discharge Protection Design with Eureka
This page is one run against one query. Ask Eureka your own question about electrostatic discharge protection design and every answer comes back with the patent numbers behind it.
Try EurekaThe patents everything else in this field cites
US20020064007A1 — Low substrate-noise ESD protection circuits with bi-directional silicon diodes
An integrated circuit device that includes a plurality of electrostatic discharge clamp circuits, variously coupled to VDD, VSS and transistor, having at least one bi-directional silicon diode that includes a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, responsive to either a positive electrostatic discharge or a negative electrostatic discharge to provide electrostatic discharge protection.Filed by Industrial Technology Research Institute; illustrates the bi-directional diode approach to substrate-noise suppression that recurs across later clamp designs in this corpus.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US5946177A | Circuit for electrostatic discharge protection | 395 |
| 2 | US5610790A | Method and structure for providing ESD protection for silicon on insulator integrated circuits | 201 |
| 3 | US20020130390A1 | ESD protection circuit with very low input capacitance for high-frequency I/O ports | 165 |
| 4 | US5576557A | Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits | 164 |
| 5 | US5856214A | Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits | 148 |
| 6 | US5530612A | Electrostatic discharge protection circuits using biased and terminated PNP transistor chains | 147 |
| 7 | US6078068A | Electrostatic discharge protection bus/die edge seal | 144 |
| 8 | US20080211028A1 | Electro-static discharge protection device, semiconductor device, and method for manufacturing electro-static… | 125 |
| 9 | US5440162A | ESD protection for submicron CMOS circuits | 123 |
| 10 | US6897536B2 | ESD protection circuit | 122 |
Citation counts inside a searched corpus favour older filings; read this table as a map of foundational influence, not of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the filing pattern tells a decision-maker
Three signals worth weighing before committing engineering or legal resources to this space.
The curve is flattening, not growing
From a 2018 peak of 47 filings, activity fell to 27 by the 2022 midpoint and toward zero in the still-incomplete final year. Combined with zero latest-year momentum across every major assignee in the ranking, this looks like a field where the core inventive ground has already been claimed, not one accelerating toward new topology.
Exposure concentrates in US filings
United States filings (775) outnumber the next four receiving offices combined by a wide margin, with Taiwan (124), Europe (101), China (76), WIPO (70) and Japan (46) trailing well behind. Freedom-to-operate work on ESD clamp designs should weight US prosecution history and litigation exposure first.
Foundational clamp art is decades old
The most-cited record in this corpus, US5946177A, carries 395 citations, and the next four most-cited records date from the mid-1990s through 2002. New filings sit on top of a well-established SCR and LVTSCR clamp foundation rather than displacing it.
Collaboration is limited and localised
Only 10 co-assignee pairs appear across the dataset, the strongest being a foundry paired with a university partner at 4 joint filings. Most patenting in this field happens under a single assignee rather than through joint ventures or foundry-fabless co-filing.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to electrostatic discharge protection design, with the prior art for and against each one.
Who is filing, and where activity has stalled
The assignee ranking is led by large foundries, IDMs and a research institute, but the momentum column tells the sharper story: none of the leading filers show latest-year activity in this dataset.
Foundries hold volume, not recent momentum
Taiwan-based foundry and IDM assignees appear repeatedly among the top filers and among the co-assignee pairs, including a foundry-university pairing at 4 joint filings. Yet the recent-year momentum figures show zero new filings from these same assignees in the latest year tracked.
Established IDMs are quiet, not absent
Instruments, memory and processor makers in the ranking show substantial historical filing but no latest-year activity in the momentum data. That is consistent with a field where the clamp and trigger topology claim space is largely settled rather than one where these firms have exited ESD work entirely.
Institute filings anchor specific sub-topologies
The representative record in this dataset, on bi-directional silicon diode clamp design, was filed by a research institute rather than a commercial IDM, pointing to a pattern where institutes seed specific circuit variants that commercial assignees later build on.
| Assignee | Recent year | YoY |
|---|---|---|
| Texas Instruments Incorporated | 0 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| United Microelectronics Corporation (UMC) | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Winbond Electronics Corporation | 0 | — |
| Intel Corporation | 0 | — |
| Qualcomm Incorporated | 0 | — |
| NXP Semiconductors N.V. | 0 | — |
Where to take this analysis
This landscape shows the shape of the field; the next layer of work is claim-level and jurisdiction-specific.
Map claim scope on the top-cited patents
Read the independent claims on the five most-cited records to see exactly how narrow or broad the foundational clamp and trigger claims run, since citation count alone does not tell you claim breadth.
Explore in EurekaCheck the thinner IPC branches for filing room
H05F, H03F and H10N carry far fewer records than H01L and H02H; a targeted search inside those subclasses can confirm whether the low count reflects genuine white space or simply narrower applicability.
Run a subclass search in EurekaVerify current assignee activity beyond the filing date
Zero latest-year momentum in this ranking may reflect publication lag rather than an actual pause; cross-check recent priority filings for the assignees you are tracking before concluding they have stepped back.
Track assignee activity in EurekaCommon questions on ESD protection patents
The most-cited records in this corpus, including US5946177A and US5610790A, date from the mid-to-late 1990s and cover foundational clamp circuit and silicon-on-insulator ESD protection structures. These older, heavily-cited patents set the baseline topology that later filings build on, so any freedom-to-operate review should start there before looking at recent assignee activity. Current top filers in the ranking are large foundries, IDMs and at least one research institute, though none show latest-year filing momentum in this dataset.
Filing activity has declined from a 2018 peak of 47 to 27 by 2022, and the most recent, still-incomplete year shows filings trending toward zero, though publication lag of roughly eighteen months means the final years are always undercounted. Recent-year momentum data shows zero new filings from the leading assignees tracked. This pattern is more consistent with a maturing field where core clamp and trigger topology is already claimed than with an area still expanding into new invention.
The United States is by far the dominant receiving office in this dataset with 775 records, more than seven times China's 76 and well ahead of Taiwan (124), Europe (101), WIPO (70) and Japan (46). Any freedom-to-operate or clearance search should weight US prosecution and litigation history heavily, since that is where the bulk of enforceable claim density sits. Secondary attention to Taiwan-filed records is warranted given the concentration of foundry assignees there.
Human body model (HBM) and charged device model (CDM) claims describe protection circuits tuned to different discharge event profiles, while latch-up immunity claims address a separate failure mode where parasitic thyristor structures trigger under transient stress. This dataset groups all three under the same search because they share overlapping clamp and trigger circuitry, but a practitioner drafting new claims should treat them as distinct technical requirements with different test standards and circuit trade-offs, particularly around capacitance loading on high-frequency I/O.
IPC subclasses H05F (static electricity handling), H03F (amplifiers) and H10N (other electric solid-state devices) carry far fewer records, 24, 19 and 34 respectively, than the dominant H01L and H02H subclasses. That gap suggests thinner prior art density in areas like amplifier-integrated ESD clamp topology and static-electricity handling structures, though a targeted subclass search is needed to confirm whether the low count reflects genuine white space or simply narrower real-world applicability of those categories.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.