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Run your analysis now →https://www.patsnap.com/resources/blog/rd-blog/embedded-trace-and-fine-line-substrates-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Patent Landscape · Packaging SubstratesEmbedded Trace and Fine Line Substrate Patents: Who Leads and Where the Gaps Sit
- Concentrated at the top. Five assignees hold 64.6% of the 158 records in scope, and the ranked leaders extend to 26 companies with a long tail beyond them.
- Filings cooled after 2021. Annual filings fell from 16 in 2021 to 11 in 2024, a 31% decline over that span, after peaking at 24 in 2022.
- Semiconductor and printed-circuit classes overlap heavily. H05K and H01L each cover roughly half of all 158 records, showing most filings sit at the substrate-semiconductor boundary rather than in a single discipline.
158
Published Records
65%
Top-5 Share of All Records
-31%
Filing Growth 2021→2024
US
Leading Jurisdiction
Filing growth compares 2021 (16 records) with 2024 (11) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 158 records in scope (CR5), not by the ranked leaders only.
Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Overview
What this landscape covers
Embedded trace substrates and fine line substrates sit at the intersection of semiconductor packaging and printed-circuit manufacturing, where line width, seed layer etching and copper adhesion determine yield at the finest pitches. This landscape draws on 158 published records filed between 2015 and 2026 that reference semi-additive processing, dry film resist or related fine-line techniques alongside packaging-substrate claims. Publication lags filing by roughly 18 months, so the most recent filing years in the trend are understated and should not be read as a slowdown on their own.
The picture that emerges is a field where a handful of large electronics and packaging firms hold most of the claim space, IPC classes overlap substantially between circuit-board and semiconductor-device categories, and filing activity has settled below its 2022 peak without disappearing.
Filing activity and technology composition, 2015-2026
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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The Data
Filing trend and technology composition
Two views of the same 158 records: how filing activity moved year over year, and which IPC subclasses the claims fall under.
Annual filings, 2017-2026
Filings rose from 6 in 2017 to a peak of 24 in 2022, then declined to 11 by 2024, a 31% drop over the 2021-2024 window. 2025 and 2026 figures are still filling in due to publication lag and should not be read as a continued decline.
IPC subclass distribution
H05K (printed circuits & assemblies) and H01L (semiconductor devices) each appear in roughly half of the 158 records, confirming that most embedded trace substrate filings straddle both disciplines. Narrower classes such as C23C (coating & surface deposition) and H10N (other solid-state devices) appear in under 5% of records, marking them as comparatively under-claimed relative to the core classes.
Shares are the percentage of the 158 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.
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Representative filing and most-cited records
Representative Filing
US20150208517A1 — Embedded trace substrate and method of forming the same
AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
In one embodiment, a method for forming an embedded trace substrate includes forming a conductive layer on a carrier. A dielectric film is provided on the conductive layer. Vias are formed in the dielectric film and extend to portions of the conductive layer. A conductive pattern is formed on the dielectric layer and is electrically connected to the conductive layer through the vias. The carrier is removed and portions of the conductive layer are selectively removed to provide a plurality of bumps pads configured to protrude outwardly from the dielectric layer.Filed by Amkor Technology Singapore Holding Pte. Ltd., 2015-07-23.
Most-cited records in this landscape
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20130249075A1 | Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package | 71 |
| 2 | US20190244743A1 | Inductor component and method of manufacturing same | 44 |
| 3 | JP2016225611A | Chip inductor | 31 |
| 4 | US7589398B1 | Embedded metal features structure | 30 |
| 5 | US9171739B1 | Integrated circuit packaging system with coreless substrate and method of manufacture thereof | 26 |
| 6 | US20070232050A1 | Embedding device in substrate cavity | 19 |
| 7 | US8115307B2 | Embedding device in substrate cavity | 18 |
| 8 | US20150130021A1 | Solonoid inductor in a substrate | 17 |
| 9 | US9565774B2 | Embedded trace substrate and method of forming the same | 13 |
| 10 | US20120125667A1 | Printed circuit board and method of manufacturing the same | 12 |
Citation counts favour older records inside this corpus and should be read as a signal of influence, not current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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What the numbers mean for filing strategy
The dataset points to a field with heavy concentration at the top, a class structure split between two large IPC groups, and a filing curve that peaked several years before the cut-off.
Concentration
64.6% of 158 records
Top 5 combined share
Claim space is held by a small group
Five assignees account for 64.6% of all 158 records in scope, and the top 10 extend that to 87.3%. A new entrant is filing into a field where the leader alone holds 30 records against a fifth-place count of 13 — the gap between the top of the ranking and the middle is wide.
Based on the 26-company ranked list returned for this dataset.
Filing momentum
-31% (2021→2024)
Three-year filing change
Activity has cooled from its 2022 peak
Filings peaked at 24 in 2022, then fell from 16 in 2021 to 11 in 2024 — a 31% decline over that span. Because publication lags filing by around 18 months, the 2025-2026 counts are still incomplete and should not be read as confirming a continued fall.
2024 is the most recent year treated as complete.
Technology overlap
53.2% / 51.9%
H05K / H01L record share
Two IPC classes dominate, almost equally
H05K (printed circuits) covers 53.2% of the 158 records and H01L (semiconductor devices) covers 51.9% — since a record can carry both classes, this overlap confirms embedded trace substrate work is filed at the packaging-semiconductor boundary rather than as a standalone circuit-board technology.
Shares are of the 158-record total, not mutually exclusive.
Filing geography
90 US filings
Leading receiving office
US filings dominate the receiving-office mix
The United States receives 90 of the filings tracked here, well ahead of Europe (EPO) at 23 and WIPO/PCT at 12. Japan, Germany and Austria each account for single-digit counts, suggesting protection strategies concentrate on the US market with selective international filing.
Counts are by receiving office, not by applicant nationality.
Eureka AI Agent
Looking for what nobody has claimed yet?
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to embedded trace and fine line substrates, with the prior art for and against each one.
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Players
Who is filing, and where the field is open
The ranked leaders span large electronics manufacturers and specialist packaging suppliers, with co-filing activity limited to a handful of pairs.
Leader
30 records
Top-ranked assignee
A single leader well ahead of the field
The top-ranked assignee holds 30 of the 158 records, more than double the fifth-place count of 13. That gap suggests a filer with a sustained, multi-year programme rather than opportunistic filing.
Ranking covers 26 companies total.
Mid-field
13 records
Fifth place
A cluster of established filers
Positions two through five each hold double-digit record counts, forming a second tier of large electronics and packaging firms that between them account for most of the 64.6% top-5 share.
Combined top-5 share: 64.6% of 158 records.
Long tail
4 records
Tenth place
Activity thins out quickly past the top ten
By tenth place, record counts drop to 4, and the ranking runs to 26 companies overall — most of the field files only a handful of times, leaving room for smaller entrants to build a defensible position in narrower claim areas.
Top 10 combined: 87.3% of 158 records.
Recent-year filing momentum by assignee
| Assignee | Recent year | YoY |
|---|---|---|
| Qualcomm Inc. | 1 | 0% |
| Murata Manufacturing Co., Ltd. | 1 | — |
| Atotech Deutschland GmbH | 0 | — |
| Panasonic Intellectual Property Management Co., Ltd. | 0 | -100% |
| Shinko Electric Industries Co., Ltd. | 0 | — |
| Intel Corp. | 0 | — |
| Samsung Electro-Mechanics Co., Ltd. | 0 | — |
| LG Innotek Co., Ltd. | 0 | — |
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's Next
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, portfolio benchmarking or identifying open claim space.
Check freedom-to-operate against the top holders
With 64.6% of records held by five assignees, any new filing in core embedded trace substrate claims should be checked against their specific claim scope before drafting.
Run a freedom-to-operate check in EurekaTrack filing momentum year over year
Because 2025-2026 counts are still incomplete, monitoring how the leaders' filing rate develops post-2024 will show whether the 2021-2024 decline persists or reverses.
Set up a monitoring alert in EurekaExplore the under-claimed IPC branches
C23C and H10N sit well below the density of H05K and H01L, suggesting narrower but potentially defensible claim space in coating chemistry and solid-state integration.
Explore white space in EurekaSource: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ
Common questions on embedded trace substrate patents
The ranked list for this dataset covers 26 companies, and the leader holds 30 of the 158 records in scope — more than double the fifth-place count of 13. The top five assignees combined account for 64.6% of all records, so a small group of large electronics and packaging manufacturers controls most of the claim space. Beyond the top ten, which together hold 87.3% of records, filing activity thins out into a long tail of companies with only a handful of filings each.
Filing activity peaked at 24 records in 2022 and has since declined, falling from 16 in 2021 to 11 in 2024 — a 31% drop over that three-year span. Because publication typically lags filing by around 18 months, the 2025 and 2026 figures in any dataset are still incomplete and should not be read as evidence of a continued slowdown. 2024 is the most recent year that can reasonably be treated as a complete filing year.
Both terms are searched together in this landscape because the underlying manufacturing techniques — semi-additive processing, seed layer etching, dry film resist — overlap heavily between the two. Records are classified predominantly under H05K (printed circuits, 53.2% of records) and H01L (semiconductor devices, 51.9% of records), and many records carry both classes, indicating the two substrate types are usually claimed as part of the same packaging process rather than as separate technologies.
Narrower IPC classes such as C23C (coating and surface deposition, 4.4% of records) and H10N (other solid-state devices, 3.2% of records) show far lower filing density than the core H05K and H01L classes. This suggests specific claim territory around surface deposition chemistry and solid-state device integration within embedded trace processes remains comparatively open, though a full freedom-to-operate check against the top assignees is still needed before filing there.
The United States receives the largest share of filings in this dataset at 90 records, followed by Europe (EPO) at 23 and the WIPO/PCT route at 12. Japan, Germany and Austria each account for single-digit counts. This pattern indicates that applicants in this field prioritise US protection first, with selective filing into Europe and international PCT routes rather than broad simultaneous multi-jurisdiction coverage.
Answers are grounded in the same dataset. Derived from a Patsnap search on Embedded Trace and Fine Line Substrates covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.