EUV Lithography Yield Optimization — PatSnap Eureka
How Engineers Optimize Yield in EUV Lithography Processes
Extreme ultraviolet lithography at 13.5 nm wavelength is the definitive patterning technology for semiconductor nodes at 7 nm and below. This report maps the patent and literature landscape across five yield-critical domains — source dose control, resist engineering, overlay correction, stochastic modeling, and optical maintenance — spanning 60+ filings from 13 assignees across 7 jurisdictions from 2005 to 2026.
Why EUV Yield Is a Multidimensional Engineering Problem
EUV lithography uses plasma-generated radiation at 13.5 nm — approximately an order of magnitude shorter than 193 nm deep ultraviolet (DUV) — to print sub-20 nm features on silicon wafers using reflective optical systems. Unlike DUV, the extreme photon energy and reflective optics architecture impose unique yield constraints: photon shot noise creates stochastic defects; tin-plasma EUV sources require precise dose stabilization; reflective mirrors degrade through contamination; and overlay errors accumulate through thermally induced mirror distortions.
Yield-optimization strategies cluster across five interlinked technical domains: EUV source dose control and plasma management; photoresist materials and underlayer engineering; overlay error correction; illumination uniformity and optical system maintenance; and stochastic modeling and process window simulation. The literature spans foundational work from 2005 through actively pending filings dated into early 2026, representing a technically mature yet rapidly evolving field. According to the IRDS 2021 roadmap, stochastic effects will require roughly triple the resist dose over the following decade — framing the central yield challenge going forward.
The 5 nm node process flow confirms EUV as the first technology generation where single-exposure EUV replaces multi-patterning for over 10 critical layers, including fin pitch (22–27 nm), contact-poly pitch (48–55 nm), and minimum metal pitch (30–36 nm). For DRAM, 16 nm devices are cited as within reach of 2018-era EUV source performance. PatSnap Analytics enables teams to map these innovation clusters systematically across jurisdictions and assignees.
Four Eras of EUV Yield Innovation: 2005–2026
From foundational plasma physics to mirror-deterioration-aware illumination rendering — how the EUV yield engineering agenda has evolved across two decades of patent filings.
EUV Yield Innovation: Filing Distribution and Dose Reduction Landscape
Patent filing counts by technology cluster and the emerging dose-reduction approaches converging across three independent R&D programmes in 2024–2025.
Patent Filings by Technology Cluster
Overlay correction (Samsung-led) and source dose control (TSMC-led) account for the largest share of retrieved filings; materials and underlayer innovation is more broadly distributed.
EUV Dose Reduction: Three Converging Approaches (2024–2025)
Intel, Lam Research, and ASM IP independently converged on dose reduction between 2024 and 2025. Intel’s UV co-exposure achieves ~35 mJ reduction from a ~90 mJ baseline.
Five Yield-Critical Domains in EUV Lithography
Patent innovation in EUV yield optimization clusters across five interlinked technical domains, each with distinct assignee concentration and IP accessibility profiles.
EUV Source Dose Control and Plasma Stabilization
ASML’s approach manipulates the conversion efficiency of laser energy into EUV plasma radiation by adjusting laser pulse timing, pre-pulse energy, and main-beam displacement — enabling both positive and negative dose corrections without sacrificing photon symmetry. TSMC extended this operationally by computing a “dose margin” (a reserve of droplet pulses beyond the nominal dose) encoded as a count of reserve tin-droplet groups (Nm) supplementing the primary dose droplets (Nd). TSMC’s 2023 filings introduced 3D laser beam profiling and EUV energy distribution mapping for real-time source correction. PatSnap Analytics can map this patent family across all five jurisdictions.
TSMC · ASML · 5 jurisdictionsPhotoresist Engineering and Underlayer Stack Optimization
Chemically amplified resists (CARs) remain the production baseline but suffer from stochastic acid-diffusion blur that degrades LER at sub-30 nm pitches. Metal oxide resists address sensitivity limitations through inorganic photon absorption with high EUV cross-sections, including tin-based and hafnium-based chemistries. Lam Research’s PECVD multilayer stacks provide atomically smooth interfaces (roughness below one monolayer) to reduce image transfer noise. IBM’s ion implantation pattern transfer uses selective ion doping of exposed hardmask regions to prevent micro-bridging from resist residue. Explore PatSnap for materials R&D.
Lam Research · ASM IP · IBM · IMECOverlay Error Correction at Sub-10 nm Nodes
At sub-10 nm nodes, overlay error — the misalignment between successive patterned layers — is a direct yield killer. Samsung Electronics is the dominant filer in this cluster, with at least six distinct US patents (2018–2026) and one KR patent. The core mechanism exploits parameter correlations: Samsung’s apparatus measures a second overlay parameter (e.g., stage position error) correlated with the first (e.g., pattern overlay error) and corrects the first through the second, reducing metrology latency. A complementary approach irradiates projection optics mirrors with a secondary laser beam to control their thermal state, compensating for thermally induced curvature changes. AMD formalized yield-driven overlay target selection as early as 2007.
Samsung dominant · 14 filings · US + KRStochastic Defect Modeling and Process Window Simulation
Stochastic effects — random variations in photon absorption, acid generation, and diffusion at the nanoscale — produce defects (bridges, breaks, CD failures) even when the mean process is on target. Two Synopsys patents (2021, 2022, US) introduce defect probability distributions — not just CD mean and sigma — as the basis for source-mask optimization (SMO). A defect-probability process window replaces the conventional CD-based exposure latitude window, enabling tighter yield-loss prediction. Carl Zeiss SMT’s CD variation correction patents (2016, 2018) address systematic CD non-uniformity by correcting spatial dose variations through optics adjustment. PatSnap’s competitive intelligence tools can track Synopsys EDA filings.
Synopsys · Carl Zeiss · IRDS 2021EUV Yield Engineering: From Source Stabilization to Pattern Transfer
The three-stage yield engineering sequence — source control, resist exposure, and pattern transfer — with key innovation levers at each stage.
Five Innovation Vectors Reshaping EUV Yield Engineering
The most recent patent filings reveal a convergence on dose reduction, mirror-aware illumination, and stochastic process window redefinition as the next frontier of yield improvement.
UV-Assisted EUV Exposure (Intel, 2024–2025)
Intel Corporation’s pending US and EP filings describe applying UV light prior to EUV exposure to sensitize chemically amplified resists or organic metal-oxide films, reducing required EUV dose by approximately 35 mJ — from ~90 mJ to ~55 mJ for equivalent CD. This directly addresses the throughput-stochastics tradeoff by reducing EUV photon demand without sacrificing pattern fidelity.
Dose-Reducing Underlayer Structures (ASM IP + Tokyo Electron, 2025)
ASM IP Holding’s pending US filing describes structured underlayer materials deposited beneath EUV photoresists that reduce the EUV dose required for patterning — a deposition-level approach to dose reduction. Tokyo Electron’s concurrent work on base-layer electron flux engineering adjusts the generation rate and transport of energetic electrons from underlayer to resist, tuning photon-to-chemical-event conversion efficiency.
Who Holds the EUV Yield IP — and Where
Samsung and TSMC together account for roughly half of all retrieved patents. Materials and underlayer innovation is more broadly distributed across the supply chain.
| Assignee | Filings (retrieved) | Primary Jurisdictions | Dominant Cluster |
|---|---|---|---|
| Samsung Electronics Co., Ltd. | ~14 | US, KR | Overlay correction, illumination uniformity |
| Taiwan Semiconductor Manufacturing (TSMC) | ~13 | US, DE, CN | Source dose control, process integration |
| ASML Netherlands B.V. | ~5 | US, WO, CN, JP | Source stabilization, optical systems |
| Lam Research Corporation | ~3 | US | PECVD underlayer stacks, UV curing |
| Carl Zeiss SMT GmbH | ~3 | US, DE | CD variation correction, optical arrangement |
| International Business Machines (IBM) | ~3 | US | Ion implantation pattern transfer |
What the EUV Yield Patent Landscape Means for R&D and IP Strategy
Dose reduction is the central yield lever of the current innovation wave. Three independent technical approaches — UV sensitization (Intel), dose-reducing underlayers (ASM IP), and pre-exposure UV curing (Lam Research) — converged independently between 2024 and 2025 on the same objective: reducing EUV photon demand per wafer to simultaneously improve throughput and reduce stochastic defectivity. R&D teams should evaluate which approach is most compatible with their process integration constraints.
Overlay correction IP is heavily concentrated at Samsung Electronics. With at least 14 retrieved filings spanning US and KR jurisdictions (2018–2026), Samsung has built a dense patent thicket around correlation-based overlay parameter correction and mirror thermal management. Competitors entering this space must design around or license into this portfolio. PatSnap’s IP analytics tools can map freedom-to-operate across this cluster.
TSMC’s dose-margin framework is broadly protected across five jurisdictions (US ×2, DE ×2, CN ×2). This cross-jurisdictional coverage of the foundational plasma-condition-aware dose control approach limits freedom to operate for scanner integrators and process engineers seeking to implement similar source stabilization logic. The European Patent Office and USPTO both host active family members.
Materials and underlayer innovation is more distributed and accessible. Lam Research, ASM IP, Tokyo Electron, IMEC, and IBM each hold distinct IP positions in resist underlayer engineering, ion implantation transfer, and PECVD stack design. This distribution suggests more accessible licensing pathways and more competitive R&D space compared to the consolidated overlay and source-control clusters. PatSnap for materials R&D supports competitive analysis in this space.
Stochastic modeling tools (Synopsys) are becoming yield-critical infrastructure. As feature sizes approach the fundamental photon-statistics limit, process window engineering based on defect probability distributions — rather than traditional CD means and sigmas — will be required for accurate yield prediction. The IRDS 2021 roadmap formalizes this challenge quantitatively.
- Three independent dose-reduction approaches converged 2024–2025: Intel UV+EUV, ASM IP underlayers, Lam Research UV curing
- Samsung overlay correction IP: ~14 filings across US and KR (2018–2026) — dense patent thicket
- TSMC dose-margin framework protected in 5 jurisdictions: US ×2, DE ×2, CN ×2
- Materials cluster (Lam, ASM IP, Tokyo Electron, IMEC, IBM) shows broader distribution — more accessible licensing
- Synopsys defect-probability SMO patents (2021–2022) becoming yield-critical EDA infrastructure
- IRDS 2021 projects ~3× resist dose increase required at future nodes without chemistry changes
- 2022–2026 filings span 8+ distinct organizations across 4 jurisdictions — broad active innovation
EUV Lithography Yield Optimization — key questions answered
Stochastic effects — random variations in photon absorption, acid generation, and diffusion at the nanoscale — produce defects such as bridges, breaks, and CD failures even when the mean process is on target. The IRDS 2021 roadmap projects that resist dose must roughly triple to maintain acceptable defect rates at future nodes, unless resist chemistry or chip design changes intervene.
TSMC’s approach characterizes the plasma condition of the EUV source prior to each wafer exposure and computes a dose margin — a reserve of droplet pulses beyond the nominal dose. The dose margin is encoded as a count of reserve tin-droplet groups (Nm) supplementing the primary dose droplets (Nd), maintaining throughput stability under plasma fluctuation. This framework is protected across five jurisdictions: US ×2, DE ×2, CN ×2.
Three independent technical approaches converged between 2024 and 2025 on dose reduction: Intel Corporation’s UV+EUV co-exposure method reduces required EUV dose by approximately 35 mJ (from ~90 mJ to ~55 mJ); ASM IP Holding’s dose-reducing underlayer structures engineer photon absorption at the deposition level; and Lam Research’s pre-exposure UV curing shifts the solubility curve of organic metal-oxide films so that a reduced EUV dose achieves the same patterning outcome.
Samsung’s apparatus measures a second overlay parameter (e.g., stage position error) that is empirically correlated with the first (e.g., pattern overlay error) and corrects the first through the second — an indirect correction approach that reduces metrology latency. A complementary approach irradiates projection optics mirrors with a secondary laser beam to control their thermal state, compensating for thermally induced curvature changes that shift the projected image position. Samsung has at least 14 retrieved filings spanning US and KR jurisdictions from 2018–2026.
Synopsys’s active US patents (2021–2022) introduce defect probability distributions — not just CD mean and sigma — as the basis for source-mask optimization (SMO). A defect-probability process window replaces the conventional CD-based exposure latitude window, enabling tighter yield-loss prediction. As IRDS 2021 projects dose-tripling requirements, computational tools that identify process conditions minimizing defect probability will become a core yield-engineering enabler.
The 5 nm node process flow confirms EUV as the first technology generation where single-exposure EUV replaces multi-patterning for over 10 critical layers, including fin pitch (22–27 nm), contact-poly pitch (48–55 nm), and minimum metal pitch (30–36 nm). For DRAM, 16 nm devices are cited as within reach of 2018-era EUV source performance at 0.33 NA.
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