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Run your analysis now →Fan-Out Wafer Level Packaging redistributes I/O connections outward from the die edge using a molding compound and one or more redistribution layers (RDLs), removing the need for a laminate substrate in many designs. This landscape draws on 838 patent families published between 2015 and mid-2026, filtered to documents that combine FOWLP terminology with specific technical claims around die shift, warpage control, molding compound formulation, redistribution layers or panel-level fan-out processing. Because publication typically lags filing by around 18 months, the most recent one to two years in any trend line understate real filing activity.
The claim scope sits almost entirely inside semiconductor device classifications (H01L) crossed with the H10W grouping, with a much smaller but present cluster of antenna-integration claims (H01Q) and printed-circuit assembly claims (H05K). Receiving-office data shows the United States as the dominant filing venue, followed by China and Taiwan, which broadly tracks where advanced packaging manufacturing capacity is concentrated.
Pick a task. Every answer cites the patents behind it.
Two views of the same 838-family dataset: how filing volume has moved year over year, and how the claim space splits across IPC subclasses.
Annual filings hit 107 in 2017, the high point across the tracked period. The 2022 midpoint sits at 60 families, roughly half the peak, and the trajectory from there is flat or declining rather than recovering — a pattern consistent with a technology whose core claim space was staked out early and is now being defended rather than expanded.
H01L accounts for 836 of the 838 records and H10W for 607, meaning most families sit at the intersection of the two. Smaller but distinct pockets exist in H01Q (antenna integration, 58 records), H10P (52) and H10D/H10N (33 each), with H05K and H10B each under 15 — these smaller subclasses are where fewer prior filings occupy the space.
Shares are the percentage of the 838 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
This page is one run against one query. Ask Eureka your own question about fan-out wafer level packaging (fowlp) and every answer comes back with the patent numbers behind it.
Try EurekaDisclosed is a fan-out wafer level packaging (FOWLP) apparatus including a semiconductor die with at least one I/O connection, a first plurality of package balls in a defined layout, a first conductive layer forming a first redistribution layer coupled to those package balls, and a second conductive layer forming a second RDL with at least one conductive pillar electrically coupling the die's I/O connection to the first conductive layer — enabling the die to connect to a second plurality of package balls.Filed by Qualcomm; published 2017-12-28 as US20170373032A1.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20140203429A1 | Fan-out package structure and methods for forming the same | 619 |
| 2 | US8803306B1 | Fan-out package structure and methods for forming the same | 603 |
| 3 | US20140168014A1 | Antenna Apparatus and Method | 318 |
| 4 | CN103872012A | 天线装置和方法 | 207 |
| 5 | US20150001708A1 | Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package | 170 |
| 6 | US20130249106A1 | Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mech… | 162 |
| 7 | US20170263518A1 | Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same | 150 |
| 8 | US20150179570A1 | Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package | 127 |
| 9 | US20130341784A1 | Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package | 124 |
| 10 | US20160329299A1 | Fan-out package structure including antenna | 123 |
Citation counts are drawn from the searched corpus and favour older, foundational filings; treat them as a measure of influence on later filers rather than current commercial relevance.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →Reading the filing trend and IPC composition together points to where claim space is dense, where it is thinning out, and where citation weight is doing more historical than practical work.
The 2017 peak of 107 families has not been matched in any subsequent year; the 2022 midpoint of 60 is roughly half that peak. Combined with the publication lag, the true recent-year picture is softer than a growth story but not a collapse — it reads as a mature claim space with steady, lower-volume filing rather than an abandoned one.
H01L combined with H10W (607 records) accounts for the overwhelming majority of filings. That concentration means core structural claims — die placement, molding, basic RDL formation — are heavily prior-arted, and new filers need to differentiate on process detail or material composition rather than broad structure.
The two most-cited documents in the corpus are both early fan-out package structure filings, cited 619 and 603 times respectively. High citation counts here mark foundational influence on later filers, not current strategic importance — recent filings have not had time to accumulate comparable citation counts.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fan-out wafer level packaging (fowlp), with the prior art for and against each one.
Recent-year momentum data shows several historically active assignees recording zero filings in the latest tracked year, several with a documented -100% year-on-year change. That does not necessarily mean exit from the field — it may reflect the publication lag or a shift to trade-secret protection on process steps — but it is worth verifying before assuming continued filing activity from any single name.
United States filings (556) outnumber the next-largest venue, China (86), by more than six to one, with Taiwan (81), EPO (38), South Korea (29) and WIPO/PCT (20) rounding out the picture. This mirrors where FOWLP process and design-house activity concentrates.
The 2017 peak has not been repeated; by the 2022 midpoint, annual volume had roughly halved. New entrants should read this as an established rather than emerging claim landscape.
Several assignees with substantial filing histories in this corpus, including large integrated device manufacturers and OSATs, show zero recorded filings in the latest year, some with a -100% year-on-year change. Given the publication lag, this needs confirming against more recent filing dates before drawing conclusions about withdrawal from the space.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | -100% |
| MediaTek Inc. | 0 | — |
| Walton Advanced Engineering Inc. | 0 | -100% |
| STATS ChipPAC Pte. Ltd. | 0 | — |
| Micron Technology, Inc. | 0 | -100% |
| Qualcomm Incorporated | 0 | — |
| Advanced Semiconductor Engineering, Inc. (ASE) | 0 | — |
| Semiconductor Components Industries, LLC (ON Semiconductor) | 0 | -100% |
The dataset points to a mature, US-concentrated claim landscape with a few thinner branches. The next steps depend on whether the goal is freedom-to-operate, competitive tracking, or identifying an open filing angle.
The highest-cited records in this corpus define much of the foundational fan-out package structure claim space; any new filing in core RDL or die-encapsulation structure should be checked against them first.
Explore citation map in EurekaSeveral assignees show zero latest-year filings in this dataset; given the publication lag, confirm current filing status before treating that as a competitive signal.
Track assignee activity in EurekaAntenna-in-package integration and memory-embedded fan-out show materially fewer records than the core H01L/H10W space, suggesting room for narrower, well-drafted claims.
Run a white-space search in EurekaFan-Out Wafer Level Packaging (FOWLP) reconstitutes a die into a molding compound before applying redistribution layers, allowing I/O connections to be routed ('fanned out') beyond the physical edge of the die rather than staying within it, as standard fan-in WLP requires. This gives more room for I/O pads and package balls on the same die size, which is why it is common in RF front-end and application-processor packaging. The patent record in this dataset reflects that structural distinction: claims cluster around molding compound formulation, redistribution layer formation and die-shift control, all of which are specific to the fan-out reconstitution step rather than the die itself.
The recent-year momentum data in this dataset shows a mix of large integrated device manufacturers, foundries and OSAT (outsourced assembly and test) providers among the historically active filers, several of which show reduced or zero filing activity in the latest tracked year. Because publication lags real filing dates by roughly 18 months, current-year rankings should be treated as provisional. The most reliable read on who is actively defending claim territory right now is the combination of overall family count and recent filing trend, not citation count alone, since citation counts favour older foundational filings.
Filing volume in this dataset peaked in 2017 at 107 families and has trended down through a 2022 midpoint of 60, without recovering. This pattern is consistent with a technology whose foundational structural claims — basic die encapsulation, RDL formation, package ball layout — were staked out early, leaving later filers to compete for narrower process and materials claims rather than broad structural ones. It does not necessarily indicate declining commercial adoption of FOWLP itself, only that the rate of new patent claims in this specific claim space has slowed.
The IPC composition data shows heavy concentration in H01L and H10W, with much smaller record counts in H01Q (antenna integration), H10D, H10N, H05K and H10B. These smaller subclasses — particularly antenna-in-package integration and memory-embedded fan-out — carry noticeably fewer filings than the core structural claim space, suggesting room for narrower claims that combine FOWLP process steps with those adjacent functions. Any filing strategy targeting this white space should still be checked against the highest-cited foundational patents, since some structural elements may still be covered even in a lower-density subclass.
The United States receives the largest share of filings in this dataset at 556 records, followed by China at 86 and Taiwan at 81, with the EPO, South Korea and the WIPO/PCT route each receiving smaller numbers. This distribution tracks where major packaging foundries, OSATs and fabless design houses operate and file first. A company assessing freedom-to-operate risk should prioritise US and Taiwan filings given their volume, without ignoring the smaller but still meaningful China filing base.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.