https://www.patsnap.com/resources/blog/rd-blog/fan-out-wafer-level-packaging-fowlp-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Patent landscape · Semiconductor packaging & test
Fan-Out Wafer Level Packaging patents: who holds the redistribution-layer claim space, and where filing has gone quiet
  • Filing peaked in 2017 at 107 families and has not returned to that level since — the midpoint year, 2022, sits at 60, and the trend line points flat-to-declining rather than growing.
  • The dataset is dominated by a single IPC pairing H01L (836 of 838 records) crossed with H10W (607) — the antenna-integration branch (H01Q, 58 records) is comparatively thin.
  • Several of the most active historical filers show zero filings in the latest year including multiple assignees with a recorded -100% year-on-year change, a pattern worth checking before assuming continued activity.
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838
Published Records
70%
Top-5 Share of All Records
-6%
3-Yr Growth (lag-adjusted)
US
Leading Jurisdiction
Published byPatsnap Research··8 min readSourced from Patsnap Eureka
Overview

What this landscape covers

Fan-Out Wafer Level Packaging redistributes I/O connections outward from the die edge using a molding compound and one or more redistribution layers (RDLs), removing the need for a laminate substrate in many designs. This landscape draws on 838 patent families published between 2015 and mid-2026, filtered to documents that combine FOWLP terminology with specific technical claims around die shift, warpage control, molding compound formulation, redistribution layers or panel-level fan-out processing. Because publication typically lags filing by around 18 months, the most recent one to two years in any trend line understate real filing activity.

The claim scope sits almost entirely inside semiconductor device classifications (H01L) crossed with the H10W grouping, with a much smaller but present cluster of antenna-integration claims (H01Q) and printed-circuit assembly claims (H05K). Receiving-office data shows the United States as the dominant filing venue, followed by China and Taiwan, which broadly tracks where advanced packaging manufacturing capacity is concentrated.

Filing activity by year, 2017-2026
  1. 1TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD447
  2. 2MEDIATEK INC50
  3. 3WALTON ADVANCED ENG INC42
  4. 4STATS CHIPPAC LTD26
  5. 5MICRON TECHNOLOGY INC22
  6. 6QUALCOMM INC17
  7. 7ADVANCED SEMICON ENG INC13
  8. 8SEMICON COMPONENTS IND LLC13
  9. 9POWERTECH TECHNOLOGY INC12
  10. 10SHANGHAI YIBU SEMICON CO LTD10
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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The data

Filing trend and technology composition

Two views of the same 838-family dataset: how filing volume has moved year over year, and how the claim space splits across IPC subclasses.

Filing trend: a 2017 peak that has not been repeated

Annual filings hit 107 in 2017, the high point across the tracked period. The 2022 midpoint sits at 60 families, roughly half the peak, and the trajectory from there is flat or declining rather than recovering — a pattern consistent with a technology whose core claim space was staked out early and is now being defended rather than expanded.

Filing trend: a 2017 peak that has not been repeated030609012010720172018201920202021202220232024202502026Most recent year is partial — publication lag means later filings are not yet visible.

IPC composition: concentrated in two subclasses

H01L accounts for 836 of the 838 records and H10W for 607, meaning most families sit at the intersection of the two. Smaller but distinct pockets exist in H01Q (antenna integration, 58 records), H10P (52) and H10D/H10N (33 each), with H05K and H10B each under 15 — these smaller subclasses are where fewer prior filings occupy the space.

IPC composition: concentrated in two subclassesH01L · Semiconductor devices83699.8%H10W60772.4%H01Q · Antennas586.9%H10P526.2%H10D · Semiconductor devices (general)333.9%H10N · Other electric solid-state dev…333.9%H05K · Printed circuits & assemblies111.3%H10B · Memory device manufacture70.8%Other394.7%

Shares are the percentage of the 838 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.

Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.

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Key patents

The most-cited records in this space

Representative record
US20170373032A12017-12-28

Redistribution layer (RDL) fan-out wafer level packaging (FOWLP) structure

QUALCOMM INCORPORATED

Disclosed is a fan-out wafer level packaging (FOWLP) apparatus including a semiconductor die with at least one I/O connection, a first plurality of package balls in a defined layout, a first conductive layer forming a first redistribution layer coupled to those package balls, and a second conductive layer forming a second RDL with at least one conductive pillar electrically coupling the die's I/O connection to the first conductive layer — enabling the die to connect to a second plurality of package balls.Filed by Qualcomm; published 2017-12-28 as US20170373032A1.

US20170373032A1 — patent drawing 1US20170373032A1 — patent drawing 2
View full record
Highest-citation FOWLP patent documents
#Publication no.Patent titleCitations
1US20140203429A1Fan-out package structure and methods for forming the same619
2US8803306B1Fan-out package structure and methods for forming the same603
3US20140168014A1Antenna Apparatus and Method318
4CN103872012A天线装置和方法207
5US20150001708A1Semiconductor Device and Method of Forming Low Profile 3D Fan-Out Package170
6US20130249106A1Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mech…162
7US20170263518A1Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same150
8US20150179570A1Semiconductor Device and Method of Forming Fine Pitch RDL Over Semiconductor Die in Fan-Out Package127
9US20130341784A1Semiconductor Device and Method of Forming an Embedded SOP Fan-Out Package124
10US20160329299A1Fan-out package structure including antenna123

Citation counts are drawn from the searched corpus and favour older, foundational filings; treat them as a measure of influence on later filers rather than current commercial relevance.

Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.

Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Insights

What the numbers mean for a filing decision

Reading the filing trend and IPC composition together points to where claim space is dense, where it is thinning out, and where citation weight is doing more historical than practical work.

Filing momentum
107 → 60 → 0
peak year → midpoint → latest partial year

Volume has not recovered since 2017

The 2017 peak of 107 families has not been matched in any subsequent year; the 2022 midpoint of 60 is roughly half that peak. Combined with the publication lag, the true recent-year picture is softer than a growth story but not a collapse — it reads as a mature claim space with steady, lower-volume filing rather than an abandoned one.

Filing trend, 2017-2026
Claim concentration
836 / 838
records tagged H01L

Almost the entire dataset sits in one IPC subclass pairing

H01L combined with H10W (607 records) accounts for the overwhelming majority of filings. That concentration means core structural claims — die placement, molding, basic RDL formation — are heavily prior-arted, and new filers need to differentiate on process detail or material composition rather than broad structure.

IPC composition
Citation influence
619 & 603 citations
top two cited documents

Citation weight sits with early foundational filings

The two most-cited documents in the corpus are both early fan-out package structure filings, cited 619 and 603 times respectively. High citation counts here mark foundational influence on later filers, not current strategic importance — recent filings have not had time to accumulate comparable citation counts.

Most-cited records
Eureka AI Agent
Looking for what nobody has claimed yet?

Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fan-out wafer level packaging (fowlp), with the prior art for and against each one.

Find the white space →
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Players

Who is filing, and who has gone quiet

Recent-year momentum data shows several historically active assignees recording zero filings in the latest tracked year, several with a documented -100% year-on-year change. That does not necessarily mean exit from the field — it may reflect the publication lag or a shift to trade-secret protection on process steps — but it is worth verifying before assuming continued filing activity from any single name.

Filing venue
556 filings
United States receiving office

The US is the dominant filing venue by a wide margin

United States filings (556) outnumber the next-largest venue, China (86), by more than six to one, with Taiwan (81), EPO (38), South Korea (29) and WIPO/PCT (20) rounding out the picture. This mirrors where FOWLP process and design-house activity concentrates.

Receiving offices
Volume trend
107 (2017)
peak annual filings

Peak filing activity is now several years in the past

The 2017 peak has not been repeated; by the 2022 midpoint, annual volume had roughly halved. New entrants should read this as an established rather than emerging claim landscape.

Filing trend
Assignee activity
0 in latest year
for several previously active filers

Multiple long-standing filers show no latest-year activity

Several assignees with substantial filing histories in this corpus, including large integrated device manufacturers and OSATs, show zero recorded filings in the latest year, some with a -100% year-on-year change. Given the publication lag, this needs confirming against more recent filing dates before drawing conclusions about withdrawal from the space.

Recent-year momentum
🔍
Under-claimed sub-areas worth a closer look
Smaller IPC pockets inside this dataset suggest branches where claim density is lower than the core H01L/H10W space.
Antenna-in-package integration (H01Q overlap)Panel-level fan-out process controlWarpage-compensation molding formulationsMulti-die RDL fan-out for heterogeneous integrationMemory-embedded fan-out (H10B overlap)
Rank all filers by momentum →
Recent-year filing momentum by assignee
AssigneeRecent yearYoY
Taiwan Semiconductor Manufacturing Company (TSMC)0-100%
MediaTek Inc.0
Walton Advanced Engineering Inc.0-100%
STATS ChipPAC Pte. Ltd.0
Micron Technology, Inc.0-100%
Qualcomm Incorporated0
Advanced Semiconductor Engineering, Inc. (ASE)0
Semiconductor Components Industries, LLC (ON Semiconductor)0-100%
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's next

Where to take this

The dataset points to a mature, US-concentrated claim landscape with a few thinner branches. The next steps depend on whether the goal is freedom-to-operate, competitive tracking, or identifying an open filing angle.

Check claim scope on the top-cited documents

The highest-cited records in this corpus define much of the foundational fan-out package structure claim space; any new filing in core RDL or die-encapsulation structure should be checked against them first.

Explore citation map in Eureka

Verify recent-year assignee activity directly

Several assignees show zero latest-year filings in this dataset; given the publication lag, confirm current filing status before treating that as a competitive signal.

Track assignee activity in Eureka

Scope a filing in the thinner IPC branches

Antenna-in-package integration and memory-embedded fan-out show materially fewer records than the core H01L/H10W space, suggesting room for narrower, well-drafted claims.

Run a white-space search in Eureka
Source: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ

Common questions on FOWLP patents

Answers are grounded in the same dataset. Derived from a Patsnap search on Fan-Out Wafer Level Packaging (FOWLP) covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.

Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.

Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.

Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.