Fan-Out Wafer Level Packaging RDL Technology 2026
Fan-Out Wafer Level Packaging RDL Technology
Redistribution layer technology in FOWLP is accelerating across AI, 5G, and heterogeneous integration. This landscape maps 70+ patent and literature records spanning 2010–2026.
How FOWLP Redistribution Layers Enable Advanced Packaging
Fan-out wafer level packaging (FOWLP) solves a fundamental I/O density constraint of standard wafer level packaging. Dies are diced, reconstituted into a larger synthetic wafer alongside molding compound, and redistribution layers (RDLs) — alternating copper traces and dielectric layers — are formed to route I/O connections to a fan-out area exceeding the die boundary.
The RDL process chain encompasses metal seed layer deposition, photolithography-defined via structures, copper electroplating, and passivation sequences. Key architectural variants include single and multi-layer RDL formation, cross-wafer long-trace RDLs extending beyond 26 mm, panel-level fan-out (FOPLP), embedded passive integration, and die shift compensation during mold cure.
Application demand is accelerating in 2026 driven by 5G infrastructure, AI edge computing, IoT modules, and heterogeneous integration. The 5-in-1 FOWLP literature case demonstrates integration of one AI chip (~2,500 pins) with four memory chips for IoT modules using three-layer RDL at 10 µm/20 µm line/space, validating FOWLP as a viable AI edge packaging platform.
In this dataset, TSMC leads with 9 records covering cross-wafer RDL families from 2020–2025, followed by SJ Semiconductor (Jiangyin) Corporation with 8 records in retrieved records spanning 2022–2024, reflecting strong activity from both foundry and OSAT tiers in the FOWLP RDL space.
FOWLP RDL Patent Filing Trends and Technology Cluster Distribution
In this dataset, filings span three maturity phases from 2010 to 2026, with distinct technology clusters concentrated around RDL formation processes, cross-wafer routing, embedded passives, and panel-level packaging approaches.
Technology Cluster Distribution — FOWLP RDL Records (Dataset Snapshot)
In this dataset, the molded reconstituted wafer / die shift correction cluster and cross-wafer long-trace RDL cluster together account for the largest share of records, reflecting strong assignee focus on reconstitution process control and heterogeneous integration routing.
↗ Click bars to exploreFOWLP RDL Filing Activity by Maturity Phase (Dataset Snapshot)
In this dataset, filing volume increased markedly from the Foundational period (2010–2015) through the Development period (2016–2021), with the Maturation phase (2022–2026) showing the highest concentration of records including pending filings from Silicon Box, Samsung, and Walton Advanced Engineering.
↗ Click bars to exploreKey Application Domains for FOWLP RDL Technology
Retrieved records span five primary application domains: mobile and consumer electronics, 5G/RF and millimeter-wave communications, AI and edge computing/IoT, energy harvesting and heterogeneous microsystems, and optoelectronics.
Mobile and Consumer Electronics
FOWLP/RDL’s dominant historical use case is smartphone application processors, baseband chips, and power management ICs requiring thin, high-I/O packages. Qualcomm’s RDL FOWLP structure targets multi-ball layout configuration without changing die I/O positions. TSMC’s InFO-WLP family, referenced in the cross-wafer RDL series, first achieved high-volume deployment in mobile application processors. MediaTek’s WLCSP-with-RDL work (2017, EP) is directly targeted at mobile chipset packaging.
Consumer Semiconductors5G and Millimeter-Wave RF
GlobalFoundries’ high-density FOWLP patent (2019, US) explicitly identifies RF inductor and antenna integration requirements. A 2022 literature record addresses a double-sided four-RDL FOWLP with mega-pillar connections for 79 GHz automotive radar applications, achieving 0.82 dB insertion loss. NXP USA’s embedded ground plane structures target RF signal integrity in fan-out packages.
RF / CommunicationsAI Edge Computing and IoT
SJ Semiconductor’s filings explicitly cite 5G communications and artificial intelligence as primary design drivers. A 2021 literature case study demonstrates integration of one AI chip (~2,500 pins) with four memory chips for IoT modules using three-layer RDL at 10 µm/20 µm line/space. Silicon Box Pte. Ltd.’s pending filings (2024–2026) for high-reliability fan-out devices with additional ground layer formation represent continued investment in AI/compute-class packaging.
AI / Edge ComputingOptoelectronics and Energy Harvesting
Avago Technologies’ embedded WLP (eWLP) process series (2016, DE) explicitly targets optoelectronic devices with front- and backside optical and electrical interfaces, enabling very thin optoelectronic package configurations at high volume. A 2019 literature survey describes FOWLP and panel-level packaging as platforms for a piezo-based energy harvester with power management unit and supercapacitor, demonstrating suitability for miniaturized autonomous sensor systems.
Optoelectronics / EnergyKey Patent Assignees in FOWLP RDL Technology (Retrieved Records)
In this dataset, TSMC and SJ Semiconductor (Jiangyin) Corporation are the two most prolific filers in retrieved records, with 9 and 8 records respectively; however, these counts reflect this dataset snapshot only and do not imply overall industry-level filing dominance.
Top FOWLP RDL Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreTaiwan Semiconductor Manufacturing Co.
TSMC holds 9 records in this dataset, all US jurisdiction (including DE), with continuous prosecution from 2020 through 2025. The cross-wafer RDL family, beginning with filings in 2020 and extending to a 2025 US record, defines redistribution lines exceeding 26 mm length across a reconstructed encapsulant wafer for heterogeneous die integration. This family is the most consistently cited architecture for multi-die FOWLP in this dataset and includes the integrated fan-out (InFO) package filing from 2019.
United States / TaiwanSJ Semiconductor (Jiangyin) Corporation
SJ Semiconductor holds 8 records in this dataset, all US jurisdiction with Chinese priority applications, spanning 2022–2024. The portfolio covers fan-out wafer-level packaging structures and methods, wafer system-level fan-out packaging, and a 2024 filing on wafer system-level three-dimensional fan-out packaging with conductive connecting posts enabling package-on-package stacking. Multiple records cite 5G communications and AI as primary design drivers; patent status includes granted US and pending continuation filings.
China — CNFrontier Innovation Signals in FOWLP RDL (2023–2026 Filings)
The most recent filings in this dataset (2023–2026) point to five active frontier directions: 3D fan-out stack architectures, hybrid reconstituted panel-level packages with fine RDL, ground layer and base metal layer reliability enhancement, compact FOWLP unit architectures, and additive manufacturing for RDL formation.
3D Fan-Out Package-on-Package Stack Architecture
SJ Semiconductor’s 2024 filing introduces conductive connecting posts on the RDL second surface, enabling stacking of a second package layer on the first — creating a true 3D fan-out package-on-package (PoP) architecture with integrated patch elements and through-RDL interconnection. This extends the FOWLP platform from planar multi-die integration to vertical stacking, directly addressing the form factor requirements of AI+memory co-packaged edge modules.
Additive Manufacturing for RDL Layer Patterning
Applied Materials’ 2019–2022 filings describe using inkjet-type additive manufacturing to print patterned dielectric and conductive RDL layers with real-time die position correction, bypassing conventional photomask-based lithography. This approach is particularly compelling for handling large die shift variations in panel-level formats. The technique is represented by a WO filing (2019) and a US continuation (2022), confirming sustained prosecution interest.
FOWLP RDL Process Approaches: Photoimageable Dielectric vs. Pre-Formed ABF Lamination
Click any row to explore further.
| Dimension | Photoimageable Dielectric + Electroplating | Pre-Formed ABF Lamination + Laser Ablation |
|---|---|---|
| Primary Assignees | TSMC, SJ Semiconductor, Semiconductor Components Industries | Avago Technologies / Broadcom |
| Via Formation Method | Lithographic exposure and develop of photoimageable dielectric layer | Direct laser ablation windows in pre-formed Ajinomoto Build-up Film (ABF) |
| Dielectric Deposition | In-situ spin-coat or spray deposition over reconstituted wafer | Pre-formed film laminated onto wafer surface prior to RDL formation |
| Trace Length Capability | Supports redistribution lines exceeding 26 mm (TSMC cross-wafer RDL) | Suited for controlled-thickness single-package RDL, shorter traces |
| Die Shift Compensation | Offset correction in RDL exposure parameters post-mold cure (SJ Semiconductor) | Planarity controlled by pre-formed film; less documented die shift correction |
| Application Fit | Heterogeneous integration, AI+memory co-packaging, 5G modules | Mobile SoC, fan-out packages requiring controlled dielectric thickness |
| Under-Bump Metallization | Formed over plated Cu redistribution lines via seed layer + electroplate sequence | UBM formed subsequent to laser-ablated via window opening in ABF |
| Filing Period in Dataset | 2010–2025 (continuous prosecution active) | 2013–2016 (Avago foundational filings, Broadcom continuation) |
Frequently Asked Questions: FOWLP RDL Technology
In FOWLP, the redistribution layer (RDL) — comprising alternating conductive metal traces (typically copper) and dielectric layers — routes I/O connections from a die to an expanded package footprint exceeding the die boundary. This enables higher pin counts, multi-chip integration, and thinner form factors than conventional packaging, as described across multiple records in this dataset.
At least four distinct approaches appear in retrieved records: photoimageable dielectric plus copper electroplating (dominant, used by TSMC and SJ Semiconductor), pre-formed ABF lamination plus laser ablation (Avago/Broadcom), metal foil lamination (Adeia Semiconductor Technologies), and additive inkjet printing (Applied Materials, 2019–2022 filings).
Die shift is the positional drift of dies during the molding/encapsulation step of FOWLP reconstitution. It is a critical manufacturability risk because it misaligns die pads relative to planned RDL trace positions. Records from at least 8 distinct assignees in this dataset — including Intel, SJ Semiconductor, and the 5-in-1 FOWLP literature study — address die shift compensation by measuring offsets and adjusting RDL exposure parameters accordingly.
TSMC’s cross-wafer RDL extends redistribution lines to lengths exceeding 26 mm across a reconstructed wafer, enabling chip-to-chip signal routing within a single package without through-silicon vias (TSVs). A photoimageable dielectric layer is deposited over all package components and the encapsulant, patterned via lithography to open vias at each die’s conductive features, and metal redistribution lines are plated. This family spans at least 9 records in this dataset from 2020 through 2025.
The 2021 literature record describes integration of one AI chip (approximately 2,500 pins) with four memory chips for IoT modules using three-layer RDL at 10 µm/20 µm line/space. This validates FOWLP as a viable AI edge packaging platform and demonstrates that wafer-level RDL can support the high pin count and fine pitch required for AI accelerator co-packaging.
Samsung’s 2025 EP pending filing addresses a gap in panel-level packaging: the inability to combine large form factors with fine-pitch, high-RDL-count routing. The proposed solution reconstitutes multiple pre-formed sub-packages (interposer-lets) into a single large panel, inheriting both the precision of wafer-level RDL and the throughput economics of panel-level manufacturing.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.