Fan-Out Wafer & Panel Level Packaging 2026 — PatSnap Eureka
Fan-Out Wafer & Panel Level Packaging 2026
Fan-out wafer level packaging (FOWLP) and panel-level evolution (FOPLP) enable higher I/O density and heterogeneous integration beyond traditional substrate-based packages. Driven by 5G, AI, and IoT demand, the field is transitioning from circular wafers toward large rectangular panels.
From Wafer to Panel: The Fan-Out Packaging Landscape
Fan-out packaging embeds singulated semiconductor dies into a reconstituted molded substrate—either a round wafer or a rectangular panel—and builds thin-film redistribution layers (RDLs) that extend I/O connections beyond the original die boundary into the surrounding mold compound area, enabling packages with higher I/O counts and smaller footprints than conventional wire-bond or flip-chip packages.
FOWLP processes on reconstituted circular substrates up to 300–330 mm in diameter using established semiconductor fab tooling. STMicroelectronics International N.V. established foundational FOWLP architecture in 2010. FOPLP transitions to large rectangular panel substrates—analogous to PCB or display panel manufacturing—to increase die-per-substrate throughput and reduce per-unit cost.
Core sub-domains across the dataset include RDL architecture and formation; warpage control and mechanical management; heterogeneous and 3D die integration; passive component embedding; antenna-in-package (AiP); and format-scale transitions from wafer to panel. The field divides into three evolutionary phases: Early Foundation (2009–2013), Development and Diversification (2014–2019), and Maturation and Panel-Scale Transition (2020–2026).
The most recent filings—dated as late as February 2026—signal that the field remains highly active. In this dataset, SJ Semiconductor (Jiangyin) Corporation accounts for the highest filing count with 9 records, followed by Intel Corporation, onsemi, and Samsung Electronics each with 5 records in retrieved records. Innovation is distributed across a multi-polar ecosystem rather than concentrated in a single player.
Technology Clusters and Filing Trends
Analysis of retrieved records reveals four primary technology clusters with warpage control representing the most heavily prosecuted domain in this dataset, and post-2020 filings showing significant acceleration in panel-level and 3D heterogeneous integration patents.
Patent Records by Technology Cluster (This Dataset)
Warpage control and RDL architecture each account for the largest shares of retrieved records in this dataset, reflecting their status as the two most contested engineering challenges in FOWLP/FOPLP development.
↗ Click bars to exploreFiling Activity by Evolutionary Phase (Retrieved Records)
Post-2020 filings represent the most active period in this dataset, with Chinese-origin assignees and hybrid panel-level architectures driving the majority of new patent prosecution through 2026 in retrieved records.
↗ Click bars to exploreKey Application Domains for FOWLP and FOPLP Technology
Fan-out packaging patents in this dataset explicitly target four primary application domains: mobile and consumer electronics, 5G communications and AI processing, millimeter-wave and RF/radar modules, and IoT edge computing—each placing distinct demands on I/O density, thermal management, and package form factor.
Mobile & Consumer Electronics
Qualcomm’s 2017 improved topology patents explicitly cite “the explosive growth of the smartphone market” as the primary motivation. IBM’s IR-assisted debonding work (2017, US) identifies smartphones and tablets as primary end markets. Dialog Semiconductor’s embedded RC film patents target power management ICs for mobile platforms.
High-Volume Mobile5G Communications & AI Processing
SJ Semiconductor’s wafer system-level fan-out family (2022–2024, US) is specifically designed for 5G and AI chips requiring hundreds of ultra-fine-pitch pads and extremely high data throughput. A 5-in-1 FOWLP literature study (2021) demonstrates AI chip integration with approximately 2,500 pins and four memory chips in a 31×31 mm form factor.
5G & AI ComputeMillimeter-Wave & RF/Radar Modules
Fraunhofer’s wafer-level antenna patents (2018 and 2024, DE jurisdiction) integrate antenna layer, shielding layer, and rewiring layer within a single wafer-level package for RF applications. A 2022 literature study documents a 12×12 mm FOWLP-AiP for USRR automotive radar with a 1×3 aperture-coupled antenna array verified at 79 GHz.
RF & Radar AiPIoT Edge Computing & Energy Harvesting
A 2019 literature review describes FOWLP and FOPLP as platforms for a miniaturized IoT energy harvester integrating a piezo harvester, power management unit, and supercapacitor. The 2021 5-in-1 FOWLP literature documents a packaged AI edge computing module in a 31×31 mm form factor combining one AI chip with four memory chips.
IoT & Edge AILeading Assignees in Fan-Out Packaging — Dataset Snapshot
In this dataset, SJ Semiconductor (Jiangyin) Corporation accounts for the highest filing count with 9 records, followed by Intel Corporation, onsemi, and Samsung Electronics each with 5 records in retrieved records. Innovation is distributed across a multi-polar ecosystem spanning US, Chinese, Korean, European, and Singaporean assignees rather than concentrated in any single player.
Top Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreSJ Semiconductor (Jiangyin) Corporation
SJ Semiconductor holds the highest filing count in this dataset with 9 retrieved records, with CN priority filings starting November 2020 and US national phase entries through 2024. Their portfolio spans wafer system-level fan-out structures, 3D stacking for AI and 5G chips, and a 2024 filing integrating millimeter-wave antennas, GPU, PMU, DDR, flash memory, and filters within a single molding-layer IPD structure. Filed patents include active US grants and pending continuations as of 2024.
China — CN (US filings)Intel Corporation
Intel accounts for 5 records in this dataset, all stemming from a foundational FOPLP warpage control family originating from a May 2018 US filing (Ser. No. 15/969,564), with continuations published through 2024 including a WO filing. Their patents consistently address structural warpage compensation techniques for panel-format packages and represent one of the broadest single-family portfolios on FOPLP manufacturability in retrieved records. All five publications remain active as of the dataset cutoff.
United StatesKey Emerging Directions in Fan-Out Packaging (2023–2026)
The most recent filings in this dataset—dated through February 2026—reveal five distinct emerging technical directions, each addressing a specific engineering barrier to the next generation of FOWLP and FOPLP production.
Hybrid FOWLP-to-FOPLP Reconstitution Architecture
Samsung Electronics’ 2025 filings (US and EP) introduce a two-stage process: first building fine-feature FOWLP sub-packages at wafer level, then reconstituting them into a large FOPLP panel. Samsung’s CN filing references target panel sizes up to 600×600 mm while maintaining fine RDL line/space from the wafer-level sub-package stage. This hybrid approach directly addresses FOPLP’s fundamental limitation of coarser RDL L/S compared to wafer-level processing.
GND Layer and Via-Enhanced Structures for AI Thermal Management
Silicon Box Pte. Ltd. (Singapore) is filing a series of patents (2024 US, 2025 and 2026 EP pending) focused on GND layer formation and preformed metal via structures to improve thermal dissipation and signal integrity in fan-out packages. These designs specifically target AI accelerator dies with high power density—a critical unresolved challenge as AI chip TDPs continue to rise in advanced packaging.
FOWLP vs. FOPLP: Key Technical and Strategic Dimensions
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| Dimension | FOWLP (Wafer Level) | FOPLP (Panel Level) |
|---|---|---|
| Substrate Format | Circular reconstituted wafer, up to 300–330 mm diameter | Rectangular panel substrate, analogous to PCB or display panel; up to 600×600 mm referenced in Samsung 2025 CN filing |
| RDL Line/Space | Fine RDL L/S achievable using established wafer fab tooling | Coarser RDL L/S due to panel-scale processing challenges; Samsung hybrid architecture aims to resolve this by using FOWLP sub-packages |
| Warpage Challenge | Manageable on circular format; STMicroelectronics 2010 patent addresses warpage reduction | More severe at panel scale due to CTE mismatch; Intel’s foundational 2018 FOPLP warpage family (5 publications) and PowerTech’s polyimide-layer strategy both address this |
| Throughput / Cost | Established tooling but limited by circular wafer area | Panel-level processing offers 2–10× productivity improvement depending on panel size per CONTENT strategic analysis |
| Key Assignees (Dataset) | STMicroelectronics (2010, 2012), Samsung (2013–2019), onsemi (2020–2025), IBM (2017–2020) | Intel (2018–2024 family), PowerTech (2023–2024), JCET Advanced Packaging (2023), CR Runan Technologies (2025) |
| Heterogeneous Integration | SJ Semiconductor wafer system-level 3D fan-out (2022–2024); Micron dual-passivation RDL with embedded passives (2017) | Samsung hybrid reconstitution enables fine-feature sub-packages assembled at panel scale (2025); CR Runan whole-wafer embedding (2025) |
| AiP / RF Integration | Fraunhofer antenna+shielding wafer-level package (2018, 2024, DE); 12×12 mm FOWLP-AiP for 79 GHz USRR automotive radar documented in 2022 literature | Not explicitly addressed in panel-level AiP patents within this dataset; remains primarily wafer-level domain |
| Maturity in Dataset | Foundational patents from 2010; broad multi-assignee coverage across all three evolutionary phases | Newer format; Intel family from 2018 is earliest FOPLP-specific cluster; major activity from 2020 onward in retrieved records |
Frequently Asked Questions: Fan-Out Wafer & Panel Level Packaging
FOWLP (Fan-Out Wafer Level Packaging) processes dies on reconstituted circular substrates up to 300–330 mm in diameter using established semiconductor fab tooling. FOPLP (Fan-Out Panel Level Packaging) transitions to large rectangular panel substrates—analogous to PCB or display panel manufacturing—to increase die-per-substrate throughput and reduce per-unit cost. Panel-level processing offers a 2–10× productivity improvement depending on panel size, but introduces more severe warpage challenges due to CTE mismatch at larger formats.
In this dataset, SJ Semiconductor (Jiangyin) Corporation holds the highest count with 9 records, followed by Intel Corporation, Semiconductor Components Industries (onsemi), and Samsung Electronics each with 5 records. STMicroelectronics International N.V. and STMicroelectronics Pte Ltd. together account for 4 records. These counts reflect retrieved records only and do not represent total industry output.
Warpage is the dominant manufacturability challenge in fan-out packaging at panel scale, arising from coefficient of thermal expansion (CTE) mismatch between the mold compound, die, and carrier. Intel’s FOPLP warpage family (originating from a May 2018 US filing, with five publications through 2024) addresses this through structural compensation techniques. PowerTech Technology employs an internal polyimide layer with chip-opening architecture to control FOPLP warpage without increasing package height. JCET Advanced Packaging uses a controlled aperture-to-region area ratio of 0.5–2:1 to balance modulus mismatch.
Samsung Electronics’ 2025 US and EP filings introduce a two-stage hybrid process: first building fine-feature FOWLP sub-packages at wafer level, then reconstituting them into a large FOPLP panel. Samsung’s CN filing references target panel sizes up to 600×600 mm while maintaining fine RDL line/space from the wafer-level sub-package stage. This approach directly addresses FOPLP’s fundamental limitation of coarser RDL L/S compared to wafer-level processing, while retaining panel-scale throughput advantages.
Retrieved patents explicitly target four primary domains. Mobile and consumer electronics: Qualcomm (2017) cites smartphone market growth; IBM (2017) identifies smartphones and tablets as end markets. 5G and AI processing: SJ Semiconductor’s 2022–2024 family targets chips requiring hundreds of ultra-fine-pitch pads. Millimeter-wave and RF/radar: Fraunhofer’s DE patents (2018, 2024) cover antenna-in-package with shielding for RF applications; a 2022 literature study documents a 12×12 mm FOWLP-AiP for 79 GHz automotive radar. IoT and edge AI: a 2021 literature study demonstrates a 31×31 mm 5-in-1 FOWLP with one AI chip and four memory chips.
Three alternative RDL formation approaches are documented in recent retrieved records. A*STAR’s 2020 US patent introduces copper damascene RDL formation as an alternative to semi-additive plating, targeting finer line/space resolution. Walton Advanced Engineering’s 2025 and 2026 US pending patents use metal paste filled into dielectric slots as a lower-cost, more environmentally sustainable alternative to conventional electroplating—targeting cost reduction and sustainability in high-volume manufacturing. SJ Semiconductor’s 2024 US filing integrates RDL with millimeter-wave antennas, GPU, PMU, DDR, flash, and filters within a single molding-layer IPD structure.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.