Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →Filing growth compares 2021 (30 records) with 2024 (21) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 244 records in scope (CR5), not by the ranked leaders only.
Fault injection covers a family of physical attacks — voltage glitching, clock glitching, laser fault injection and electromagnetic pulse injection — used to force a chip into an unintended state and bypass its security checks. The countermeasure side of the same search captures redundant computation, control-flow integrity checks and photodiode sensing, the detection and recovery mechanisms vendors build in response. This dataset spans 244 published records from 2015 through the 2026-07-31 cut-off, drawn from a search string that requires both an attack term and a countermeasure or detection term in the same record.
Because publication lags filing by roughly 18 months, the 2025 and 2026 figures in any trend line are undercounts by construction; 2024 is the most recent year that can be read as complete. The dataset draws primarily on secure-element and smart-card vendors, general semiconductor makers and a smaller set of payment-terminal and cloud-hardware filers, which shows up clearly in the IPC composition below.
Pick a task. Every answer cites the patents behind it.
Two views of the same 244 records: filing activity by year, and the IPC subclasses those records carry. Because a single record can carry several IPC classes, the class shares below sum to well over 100% of the record total — that is expected and is not a sign of double-counting.
Annual filings climbed from 17 in 2017 to a peak of 42 in 2022, then declined to 21 by 2024 — a -30% move from 2021's 30 filings over that three-year span. Treat 2025 and 2026 as still filling in rather than as evidence of a further slowdown.
G06F (electric digital data processing) appears in 55.7% of the 244 records and H04L (digital information transmission) in 28.3%, with G01R (electric and magnetic measurement) at 20.9% covering the physical glitch-detection circuitry itself. G07F (coin-freed and vending apparatus), the payment-terminal-specific class, sits at only 4.1% — a thin slice relative to how often fault injection is discussed as a payment-security threat.
Shares are the percentage of the 244 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
This page is one run against one query. Ask Eureka your own question about fault injection and countermeasures and every answer comes back with the patent numbers behind it.
Try EurekaThe system on chip carries a memory controller with clock synchronization circuitry built on a locked loop, paired with a voltage glitch attack detector that monitors the clock synchronization signal and checks whether it is nominal or characteristic of a voltage glitch attack. The detector can be implemented as software running on the processing unit rather than dedicated analog hardware.Other embodiments are disclosed beyond the monitoring circuit described here.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20030226082A1 | Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack | 81 |
| 2 | US20080061843A1 | Detecting voltage glitches | 42 |
| 3 | US6880752B2 | System for testing, verifying legitimacy of smart card in-situ and for storing data therein | 38 |
| 4 | US20150346246A1 | Method and Apparatus for Supply Voltage Glitch Detection in a Monolithic Integrated Circuit Device | 37 |
| 5 | US20210004461A1 | Quantitative digital sensor | 31 |
| 6 | US20170228562A1 | Circuit protection system and method | 29 |
| 7 | US10474846B1 | Processor power supply glitch detection | 25 |
| 8 | US20190005269A1 | Automatic Reset Filter Deactivation During Critical Security Processes | 24 |
| 9 | US20170141911A1 | Split-and-merge approach to protect against DFA attacks | 23 |
| 10 | US7085979B2 | Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack | 23 |
Citation counts reflect influence within the searched corpus and favour older filings; they are not a measure of current commercial importance.
Each row carries its publication number; clicking a row searches Eureka by that number.
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →Three patterns worth acting on before drafting claims in this space.
One assignee leads at 29 records, with fifth place at 11 and tenth at 8 — a steep drop-off after the top few. The other 49 ranked assignees split the remainder in small counts, which means most of the field's claim space is still held in narrow, single-vendor slices rather than blocked by a handful of broad players.
Filings rose from 17 in 2017 to 42 in 2022, then fell to 21 by 2024. That decline reads as core detection mechanisms (voltage and clock glitch sensing) becoming well-claimed rather than the underlying attack surface losing relevance — new work is more likely to sit in adjacent, less-crowded branches.
G06F (digital processing) and H04L (transmission) dominate the corpus, while G07F (coin-freed/vending apparatus, the class covering payment terminals) sits at just 10 of 244 records. For a threat model frequently discussed in point-of-sale and smart-card contexts, terminal-specific claim language is comparatively open.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fault injection and countermeasures, with the prior art for and against each one.
Filing is led by secure-element and smart-card vendors alongside general semiconductor makers, with several previously active filers showing no filings in the latest tracked year.
The top-ranked assignee holds 29 of the 244 records in scope, well ahead of fifth place at 11 — but that still leaves 215 records spread across 58 other assignees, most in single digits.
Several assignees that were active earlier in the window, including NXP, Nuvoton, Nordic Semiconductor and Thales DIS France, show zero filings in the latest tracked year. This is consistent with the broader 2021-2024 decline and with publication lag, not necessarily with those firms exiting the space.
Only six co-assignee pairs appear in the dataset, the strongest tied to a single company's named inventors rather than cross-company joint filings. This is a field of largely independent filers rather than one built on formal patent-pooling or joint-development arrangements.
| Assignee | Recent year | YoY |
|---|---|---|
| NXP B.V. | 0 | -100% |
| Nuvoton Technology Corporation | 0 | -100% |
| Secure IC | 0 | -100% |
| NDS Limited | 0 | — |
| Thales DIS France SA | 0 | — |
| Nordic Semiconductor | 0 | — |
| Google LLC | 0 | — |
| Intel Corporation | 0 | — |
The landscape points to specific next steps depending on whether the goal is freedom-to-operate, portfolio-building or monitoring a competitor.
Before drafting claims around voltage or clock glitch detection, check them against the top 10 assignees, who together hold 59.4% of the 244 records in this landscape.
Run a freedom-to-operate check in Eureka →G07F payment-terminal claims and photodiode-based sensing sit well below the corpus average in filing density, which is where a first claim has more room to stand.
Explore white space with Eureka →Several previously active filers show zero filings in the latest tracked year; a renewed filing from any of them is worth flagging early given their earlier concentration in this space.
Set up assignee monitoring in Eureka →The dataset covers physical attacks that force a chip into an unintended state, including voltage glitching, clock glitching, laser fault injection and electromagnetic pulse injection, as captured by the search string used to build this landscape. Records are only included if they also reference a detection or countermeasure concept such as redundant computation, control-flow integrity, a photodiode sensor or a similar mechanism. This means the 244 records in scope represent the intersection of attack and defence disclosure, not every patent that merely mentions glitching in passing.
Filing is concentrated at the top: the leading assignee holds 29 of the 244 records, and the top 5 of 59 ranked assignees together account for 41.8% of all records in scope. The next tier drops off quickly, with fifth place at 11 records and tenth place at 8, meaning most of the ranked field holds only a handful of filings each. Named leaders in the underlying evidence include established secure-element and smart-card vendors alongside general semiconductor and cloud-hardware filers.
Filing peaked in 2022 at 42 records and eased to 21 by 2024, a -30% move from 2021's 30 filings, but this should not be read as the field losing relevance. Publication lags filing by roughly 18 months, so 2025 and 2026 figures in the same dataset are understated by construction and cannot yet be compared fairly to earlier years. A more likely explanation for the 2022-2024 easing is that core voltage and clock glitch detection mechanisms are now well-claimed, pushing new filing activity toward adjacent techniques rather than away from the field entirely.
The clearest gap by class share is payment-terminal-specific detection: G07F, the IPC subclass covering coin-freed and vending apparatus including payment terminals, appears in only 4.1% of the 244 records despite fault injection being a well-known threat to point-of-sale hardware. Photodiode-based laser fault injection sensing and control-flow integrity checks for embedded firmware also show thinner filing density relative to the dominant G06F and H04L classes. These branches are where a first claim has more room to stand without running into the dense prior art around core voltage-glitch detection.
US20240005045A1, filed by Thales DIS France with a 2024-01-04 date, claims a system on chip that detects voltage glitch attacks by monitoring a clock synchronization signal generated by locked-loop circuitry and checking whether that signal matches its nominal pattern. A notable feature is that the detector can be implemented as software on the existing processing unit rather than requiring dedicated analog detection hardware, which is a narrower and more specific claim path than analog voltage-comparator detection. It does not block glitch detection built on other signal sources such as direct voltage-rail monitoring or photodiode-based sensing, since those rely on different detection circuitry entirely.
Go past this page: query the whole fault injection and countermeasures corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.
Help us improve
Something wrong, out of date, or missing on this page? Tell us and it goes straight to the team that maintains it.
This page