FD-SOI Advanced Materials Patents: Leaders, Trends & White Space 2026
- A small, concentrated dataset. just 13 patent families sit inside this search string, filed across EPO, France, WIPO and the US — this is a narrow, specialist claim space, not a crowded field.
- Filing has already peaked. activity crested at 5 families in 2019 and has not returned to that level since, suggesting the core buried-oxide and strained-SOI claims were staked out early.
- RF-specific device architecture stands out. the most-cited record in the set claims a multi-finger RF nFET with a buried stressor layer — a strong signal that RF power applications are where current value sits.
What this patent set covers
FD-SOI advanced materials patenting sits at the intersection of substrate engineering and device architecture: claims here cover ultra-thin SOI wafers, buried oxide engineering, and strained SOI material, combined with fully depleted transistor structures. The search string pulls documents classified under core semiconductor device IPC codes (H01L21/762, H01L27/12, H01L21/84), which is where substrate-level and isolation-level claims are typically filed rather than at the process-tool or equipment level. This is a materials-and-structure view of FD-SOI, not a lithography or deposition-tool view.
The dataset is small — 13 published families across a roughly decade-long window — which makes it a specialist corner of the broader FD-SOI landscape rather than a mainstream battleground. Publication naturally lags filing by around 18 months, so the most recent years in any trend understate real activity; treat the last one to two years as provisional rather than a signal of decline.
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Filing trend and technology mix
Thirteen families is enough to show a shape, not enough to support fine-grained year-over-year claims. Read the trend as a directional signal and the IPC mix as where within semiconductor devices the claims actually sit.
A single peak, then plateau
Filings were at zero in 2017, rose to a peak of 5 in 2019, and by the 2022 midpoint had settled to 4 — flat-to-declining rather than accelerating. There is no second wave visible in this window; whoever staked out core buried-oxide and strained-SOI claims did so early, and later filers are layering device-level refinements on top rather than opening new substrate ground.
Concentrated in core device classes
Every record in the set carries H01L (semiconductor devices), the parent classification for FD-SOI substrate and transistor claims. Secondary classification into H10P and H10W (4 records each) and a single H10D record indicates most filings also touch newer device/architecture subclasses rather than staying purely at the materials level — consistent with claims that pair a substrate feature with a specific transistor or RF structure.
Shares are the percentage of the 13 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on FD-SOI Advanced Materials with Eureka
This page is one run against one query. Ask Eureka your own question about fd-soi advanced materials and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this set
Multi-Finger RF nFET Having Buried Stressor Layer and Isolation Trenches Between Gates
An RF MOSFET built with pluralities of gate, source and drain fingers connected through respective mandrels, arranged so adjacent unit cells share isolation structure. The claims center on a buried stressor layer combined with isolation trenches between gates — a substrate-and-structure combination aimed squarely at RF power performance rather than general-purpose logic.Filed by Acorn Semi, LLC; published 2023-03-23.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | FR3091004A1 | STRUCTURE DE TYPE SEMI-CONDUCTEUR POUR APPLICATIONS DIGITALES ET RADIOFRÉQUENCES | 4 |
| 2 | US20230093111A1 | MULTI-FINGER RF nFET HAVING BURIED STRESSOR LAYER AND ISOLATION TRENCHES BETWEEN GATES | 3 |
Citation counts inside a searched corpus favour older documents that have had more time to accumulate citations — treat this as a signal of influence on the field, not of current commercial importance.
Publication numbers are shown where the record carries one (2 of 2 rows); clicking a row searches Eureka by that number.
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With only 13 families, every structural observation here is a pattern in a small sample — useful for orienting a search strategy, not for forecasting market share.
Activity crested and has not returned
The dataset's single peak year sits at 5 families in 2019, with the 2022 midpoint down to 4. No later year approaches the peak, which is unusual for a technology area still under active development — it points to core claims being staked early and filed against since.
European filing routes dominate
Europe (EPO), France directly, and the WIPO/PCT route each carry 4 filings, against a single US filing. That split suggests the active filers in this specific claim combination are weighted toward European entities using PCT or direct European routes rather than filing US-first.
Substrate claims paired with device architecture
Every record sits in H01L, but roughly a third also carry H10P or H10W codes — indicating claims that combine a buried-oxide or strained-SOI substrate feature with a specific transistor or RF device structure, rather than claiming the material alone.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fd-soi advanced materials, with the prior art for and against each one.
Who is active, and where the room to file remains
The assignee ranking here is short and thin — 13 families spread across a small number of filers, with recent-year activity flat for the two most visible names.
No fresh activity from the visible leaders
The two most identifiable assignees in the ranking recorded zero filings in the latest year captured by this dataset. Given the 18-month publication lag, this understates true recent activity, but it is also consistent with the broader trend of a 2019 peak that has not been repeated.
A narrow, specialist filer base
With only 13 families in the entire ranking, this is not a market with a dominant player pulling ahead of a crowd — it is a small set of specialist filers, some with a single family, working a tightly defined claim combination of substrate engineering and RF/logic device structure.
European-centred filing strategy
The near-even split between EPO, France and WIPO/PCT routes, against a single US filing, suggests the active filer base is protecting FD-SOI substrate and device claims primarily in Europe, with US coverage sought more selectively.
| Assignee | Recent year | YoY |
|---|---|---|
| Soitec | 0 | — |
| ACORN SEMI LLC | 0 | — |
Where to take this analysis
A 13-family dataset is a starting map, not a final answer. The next steps depend on whether the goal is freedom-to-operate, portfolio benchmarking, or spotting where a new filing could still land clean claim space.
Run a freedom-to-operate check on RF stressor claims
If a design touches buried stressor layers combined with isolation trenches, the most-cited document in this set is the first one to clear before committing to a device architecture.
Explore in EurekaModel the white space chips against your own roadmap
The under-claimed sub-areas flagged here are a starting hypothesis, not a guarantee of openness — cross-check them against a live, broader search before filing.
Explore in EurekaTrack the European filer base for shifts in strategy
With EPO, France and WIPO routes tied at 4 filings each and the US at just 1, a change in that ratio would be an early signal of a shift in where FD-SOI substrate claims are being protected.
Explore in EurekaCommon questions about FD-SOI advanced materials patents
This dataset is scoped specifically to fully depleted SOI combined with material-level features such as ultra-thin SOI wafers, buried oxide engineering and strained SOI material, filtered to core semiconductor device IPC classes. General SOI patenting is a much larger field covering partially depleted devices, memory applications and process equipment. The narrower FD-SOI advanced materials scope is why this set only contains 13 families — it excludes the broader SOI ecosystem and focuses on substrate-and-device claim combinations.
Based on this dataset, filing peaked at 5 families in 2019 and had settled to 4 by the 2022 midpoint, with no later year matching the 2019 peak. That is a flat-to-declining pattern rather than sustained growth. Because publication lags filing by roughly 18 months, the most recent one to two years should be read as provisional rather than as confirmation of a real slowdown.
In this dataset, Europe (EPO), France directly, and the WIPO/PCT route are tied at 4 filings each, with a single filing at the US receiving office. That points to a filer base weighted toward protecting these claims in Europe first, using either direct national filing or the PCT route, with US coverage sought more selectively. Any freedom-to-operate check should therefore prioritise European prosecution history.
US20230093111A1, assigned to Acorn Semi, LLC and published in 2023, claims a multi-finger RF nFET architecture with gate, source and drain fingers connected through mandrels, built on a buried stressor layer with isolation trenches between gates. It is the most-cited record in this dataset. Anyone designing an RF power device on strained or stressor-engineered SOI substrates should review this document's claim scope before finalising a device architecture, since it combines a substrate feature with a specific multi-finger layout.
The IPC and citation pattern in this dataset points to thinner coverage in areas such as strained-SOI RF stressor integration outside the specific multi-finger layout already claimed, buried oxide thickness gradients used for isolation trench design, and dual-domain digital/RF substrate structures. These are starting hypotheses drawn from a 13-family set, not a guarantee of open claim space, so any filing strategy built on them should be checked against a live, broader search first.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.