FD-SOI Patents: Who Leads, Where the Gaps Are 2026
- Filings peaked in 2019 at 18 and have since flattened, with the 2022 midpoint at 8 — the field is consolidating around existing claims rather than expanding.
- The most-cited foundational patents date back to the early 2000s, meaning the architecture's core claim space (mixed body thickness, partially/fully depleted co-integration) was staked out long before the current filer set arrived.
- Every tracked leading assignee shows zero filings in the latest year, consistent with the usual 18-month publication lag rather than an actual pullback from the technology.
What the FD-SOI patent record actually covers
FD-SOI — fully depleted silicon-on-insulator — transistor architecture separates itself from bulk CMOS through an ultra-thin body over a buried oxide layer, enabling back-gate body biasing as a live design lever rather than a static substrate property. The 205 patent families tracked here span claims on buried oxide formation, back-gate control schemes, and mixed body-thickness integration on a common substrate. Search scope was narrowed to records combining FD-SOI or fully depleted SOI terminology with body-biasing, buried-oxide, or back-gate claim language, filtered against the semiconductor-device IPC classes where these claims are actually granted.
Filing activity runs from 2017 through a partial 2026, concentrated overwhelmingly in the core H01L semiconductor-device classification, with secondary claim activity in memory-device manufacture and pulse/logic circuits. Publication lags filing by roughly 18 months, so the most recent one to two years in any trend understate real filing activity.
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Filing trend and technology composition
The dataset shows a technology that built its claim base in the late 2010s and has since settled into steady, unspectacular filing rather than continued expansion.
A peak-then-plateau filing curve
Annual filings rose to a peak of 18 in 2019, fell back toward the midpoint of 8 by 2022, and the partial 2026 count of 1 reflects the publication lag rather than a collapse in interest. Read as a signal, this pattern says the foundational claim space filled up first, and subsequent filings are increasingly incremental refinements rather than new architectural bets.
Concentration in core device claims, thinner elsewhere
H01L semiconductor-device claims cover 201 of 205 records, essentially the entire corpus, with H10D general semiconductor-device claims a distant second at 72. Memory-device manufacture (H10B, 21) and static/digital memory (G11C, 16) show FD-SOI's use as a memory-integration substrate, while pulse-technique and logic-circuit claims (H03K, 11) mark where body-biasing is being claimed as a circuit-design tool rather than a device structure.
Shares are the percentage of the 205 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on FD-SOI Technology Landscape with Eureka
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Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
The technique bonds a semiconductor-on-buried-oxide wafer to a second wafer carrying a ferroelectric layer, placing that layer directly in the back-gate stack of a fully depleted SOI transistor. This turns the back-gate itself into a non-volatile, field-switchable element rather than a passive bias terminal.Filed by International Business Machines Corporation; published 2020-02-27.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6867433B2 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multip… | 328 |
| 2 | US20030032262A1 | Silicon on insulator DRAM process utilizing both fully and partially depleted devices | 248 |
| 3 | US20090302387A1 | Integrated circuit chip with FETS having mixed body thicknesses and method of manufacture thereof | 237 |
| 4 | US11127738B2 | Back biasing of FD-SOI circuit blocks | 160 |
| 5 | US6222234B1 | Semiconductor device having partially and fully depleted SOI elements on a common substrate | 160 |
| 6 | US6787424B1 | Fully depleted SOI transistor with elevated source and drain | 156 |
| 7 | US6452229B1 | Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication | 124 |
| 8 | US7498637B2 | Semiconductor memory | 122 |
| 9 | US20050093067A1 | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multip… | 118 |
| 10 | US6509234B1 | Method of fabricating an ultra-thin fully depleted SOI device with T-shaped gate | 83 |
Citation counts inside this corpus favour older filings that later filers had to cite around; treat them as a measure of influence on the field, not of current commercial relevance.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns in the data matter more than the raw counts: where claim density sits, how old the blocking art is, and how concentrated receiving-office activity is.
Core device claims are nearly saturated
Almost every record in this corpus falls under the core semiconductor-device IPC class, meaning basic buried-oxide and body-thickness structural claims are heavily occupied. New filings here compete directly with an existing, dense prior-art base rather than opening fresh ground.
The oldest patents still set the boundaries
The most-cited record, on strained-channel partially/fully depleted and multi-gate transistor integration, and several other high-citation patents predate 2010. Anyone drafting new body-biasing or mixed-body-thickness claims needs freedom-to-operate analysis against this older art first.
Filing activity is US-centred with a Japan/Europe tail
The United States receives roughly two-thirds of tracked filings, with Japan, the EPO and China each taking single-digit-to-low-double-digit shares. A filing strategy built only around US coverage would miss the secondary but real activity in Japan and Europe.
Momentum has flattened, not accelerated
From a 2019 peak of 18 filings to a 2022 midpoint of 8, the trend is flat to declining well before the lag-affected final years are accounted for. This is a mature claim landscape, not an emerging one.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fd-soi technology landscape, with the prior art for and against each one.
Who holds the ground, and where it's shared
A small set of assignees account for most of the co-filing activity, and the strongest pairings point to foundry-and-fabless collaboration rather than single-company dominance.
GlobalFoundries anchors the densest alliance
The strongest co-assignee pair in the dataset links GlobalFoundries with STMicroelectronics, with a second, smaller pairing to IBM. This suggests joint process-integration filings rather than pure competition for the same claims.
IBM files across both device and memory claims
IBM's back-biasing patent is among the most-cited recent records in the corpus, and its co-filing activity spans both GlobalFoundries and STMicroelectronics, indicating involvement across process, circuit and memory-integration claim types.
Soitec's activity sits earlier in the window
As the substrate and wafer-bonding specialist in this space, Soitec's recent-year momentum reads as zero, consistent with the broader lag in the dataset rather than a withdrawal from buried-oxide and wafer-bonding claim work.
| Assignee | Recent year | YoY |
|---|---|---|
| GlobalFoundries Inc. | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Soitec | 0 | — |
| Advanced Micro Devices, Inc. (AMD) | 0 | — |
| STMICROELECTRONICS INC | 0 | — |
| Renesas Technology Corp. | 0 | — |
| STMicroelectronics International N.V. (Switzerland) | 0 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
Where to take this analysis
The dataset points to a mature core and a thinner set of adjacent branches. The next steps depend on whether the goal is defensive clearance or offensive filing.
Run freedom-to-operate against the oldest citations
The highest-citation records in this corpus predate 2010 and still shape what counts as novel in body-thickness and buried-oxide claims. Any new filing plan should start there, not with recent publications.
Explore prior art in EurekaTrack the co-filing alliances, not just single assignees
The strongest activity in this space runs through foundry-fabless pairings rather than isolated filers. Understanding who files jointly with whom clarifies where licensing or partnership conversations are already happening.
Map assignee networks in EurekaWatch the under-claimed circuit-side branches
Structural device claims are dense, but back-gate logic and dynamic biasing circuit claims are comparatively thin. That asymmetry is where new filings have the most room to stand on their own.
Search white space in EurekaCommon questions about FD-SOI patents
FD-SOI stands for fully depleted silicon-on-insulator, a transistor architecture where an ultra-thin semiconductor body sits over a buried oxide layer so the channel is fully depleted of charge carriers during operation. Patent claims in this space typically centre on the buried oxide layer's formation, the ultra-thin body's thickness control, and the back-gate terminal that biasing schemes use to tune threshold voltage dynamically. This differs from bulk CMOS claims, which generally address doping and well structures in a continuous substrate rather than a layered, biasable stack, and is why FD-SOI claims cluster so heavily in the semiconductor-device IPC classes rather than general process classes.
The co-assignee data shows GlobalFoundries and STMicroelectronics as the most frequently linked pair in this corpus, with IBM also appearing in multiple joint filings alongside both. Soitec appears as a substrate and wafer-bonding specialist rather than primarily a circuit-design filer. No single assignee dominates outright; the pattern is closer to a small cluster of foundry, fabless and substrate specialists filing jointly than one company controlling the field.
This is almost certainly a publication-lag artefact rather than a real drop in activity. Patent applications typically publish about 18 months after filing, so the most recent one to two years in any patent dataset will always understate true filing activity until later publications catch up. Readers should treat the final year of any trend chart, including this one, as provisional and expect the numbers to rise as more records surface.
The core structural claim space is dense: 201 of 205 tracked records fall under the primary semiconductor-device IPC class, and several of the most-cited patents date back to the early 2000s, meaning basic buried-oxide and mixed-body-thickness claims are well covered. That said, filing volume itself peaked in 2019 and has since flattened rather than grown, which suggests slower entry rather than active foreclosure. Adjacent circuit-level claims, such as back-gate logic design and dynamic multi-zone biasing, show thinner coverage and may offer more room to file a defensible new claim.
This IBM-assigned patent, published in February 2020, claims a fully depleted SOI transistor with a ferroelectric layer built into the back-gate stack, formed by bonding a buried-oxide wafer to a separate ferroelectric-layer wafer. Anyone designing a back-gate structure that uses a ferroelectric material for non-volatile or field-switchable biasing should check this claim's scope closely, since it covers both the structural placement of the ferroelectric layer and the wafer-bonding method used to create it. Workable alternatives likely involve non-ferroelectric back-gate materials or different bonding sequences that fall outside the specific claim language.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.