Low-frequency noise (LFN) in MOSFETs is classically attributed to carrier number fluctuations (ΔN) due to trapping and de-trapping at the gate oxide/silicon interface, mobility fluctuations (Δμ) driven by bulk defects, or a combination of both. In standard bulk transistors, the dominant interface is the top Si/SiO₂ gate dielectric. But FDSOI architectures introduce a second critical interface: the Si/BOX (buried oxide) boundary.

As demonstrated by IMEP-LAHC, Grenoble (2020), a multilayer gate stack flat-band voltage fluctuation model was established, revealing that the BOX and the Si-BOX interface contribute measurably to total drain current noise. Critically, this work also showed that the noise increase observed at strong inversion can be explained by the contribution of source/drain access resistance to 1/f noise — a finding with direct implications for layout and process optimization.

Research from IEEE-published Kansai University (2018) confirms that quality of both Si/SiO₂ interfaces modulates LFN characteristics. In the subthreshold regime, the weak inversion channel near the top surface is strongly influenced by top-surface interface traps, since these traps are less screened in weak inversion than in strong inversion — a finding especially consequential for ultra-low-voltage analog applications relying on subthreshold biasing.

Beyond interface traps, random telegraph noise (RTN) — discrete, bistable fluctuations in drain current caused by a single trap — emerges as an increasingly serious LFN manifestation in scaled FDSOI. Research from the Institute of Microelectronics, Chinese Academy of Sciences (2022) demonstrated that conventional RTN analysis methods designed for bulk CMOS are not directly transferable to advanced SOI-based transistors due to modified electrostatics and carrier confinement in the ultra-thin body.

The reliability dimension is underscored by Tianjin University (2021): interface traps generated by RF stress progressively worsen LFN, making stress-induced noise degradation a critical concern for mixed-signal transceivers. Semiconductor reliability analysis via PatSnap Eureka can surface these stress-LFN correlation studies rapidly.

At the circuit level, LFN is addressed through biasing strategies, topology choices, and architectural techniques. In neuromorphic and sub-threshold analog design using 28 nm FDSOI, the University of Zurich and ETH Zurich (2017) describe methods to minimize channel leakage current effects and support efficient analog computation in the pA–nA range, where 1/f noise is most problematic relative to signal levels.

Noise coupling between digital and analog domains in mixed-signal systems — distinct from transistor-level LFN but equally critical for SoC integration — was addressed by Freescale Semiconductor (2008), proposing substrate isolation through split ground rails and noise-aware cell replacement methodology. In SOI-based processes, the buried oxide itself provides inherent substrate isolation, identified as a primary reason for preferring FDSOI in mixed-signal deployments by Universiti Kebangsaan Malaysia (2013).

Low-voltage FDSOI OTA design from Northeastern University (2012) designed PMOS and NMOS differential-input OTAs in 150 nm FDSOI operating from 0.4 V, achieving gain/bandwidth/power trade-offs directly shaped by the LFN characteristics of the input differential pair — where PMOS devices typically exhibit lower flicker noise than NMOS, a guideline that also applies in FDSOI contexts. See how semiconductor teams apply these insights in production analog design.

For negative capacitance FDSOI variants, NC-FDSOI transistors achieve improved transconductance efficiency and reduced operating voltages, implying a potential pathway to improved noise figure at low power. An emerging trend is the extension of FDSOI LFN characterization to cryogenic temperatures (4 K), driven by quantum computing co-integration requirements where FDSOI is seen as a strong candidate for qubit readout electronics.

The WIPO patent database and IEEE Xplore together index the majority of the foundational FDSOI LFN literature, but PatSnap Eureka's AI-native search surfaces cross-domain connections between patent claims and academic findings that manual searches miss.