FDSOI Substrate Technology Patent Landscape 2026
FDSOI Substrate Technology Landscape 2026
Fully Depleted Silicon-On-Insulator (FDSOI) substrate technology enables low-power, high-performance CMOS scaling beyond 28nm via ultra-thin SOI layers and back-gate threshold voltage tuning. This dataset covers 70+ patent records spanning 2009–2026 across hybrid epitaxy, SiGe channel engineering, RF substrates, and emerging application domains.
FDSOI: Planar CMOS Scaling Beyond 28nm
FDSOI substrate technology is defined by a trilayer stack: a bulk silicon handle substrate, a buried oxide (BOX) dielectric layer, and an ultra-thin semiconductor top layer typically 6–20nm silicon or SiGe. Full depletion of the transistor channel without requiring doping eliminates random dopant fluctuation (RDF) effects and improves threshold voltage stability, making FDSOI a leading alternative to FinFET for energy-efficient and RF applications.
Key sub-domains identified across retrieved records include hybrid epitaxial region integration for ESD and body pickup, SiGe channel engineering for PMOS hole mobility improvement, back-gate bias architecture for dynamic threshold voltage tuning, RF and high-resistivity substrate engineering, shallow trench isolation adapted for ultra-thin SOI geometry, and multi-layer raised source/drain epitaxial structures for contact formation without BOX punch-through.
The innovation timeline spans from foundational back-gate isolation patents filed by GlobalFoundries in 2009 through a high-density process intensification phase in 2018–2021 led by Shanghai Huali and CEA, to a maturation phase in 2022–2024 where SiGe channel stacks, multi-layer S/D epitaxy, and defect reduction dominated filings. The 2025–2026 emerging phase introduces microfluidic cooling integration, ferroelectric radiation-hardened back-gate stacks, and FDSOI image sensor platforms.
Among 74 retrieved records with identifiable assignees, filing activity in this dataset is heavily concentrated in China, led by Shanghai Huali Integrated Circuit Corporation with approximately 30 distinct patent records in this dataset, followed by Reli Pingxin Microelectronics with approximately 8 records. The CN jurisdiction accounts for approximately 40 filings in retrieved records, compared to roughly 25 for the US.
Filing Trends and Technology Cluster Distribution
Analysis of retrieved FDSOI patent records reveals a clear concentration in process-module-level innovations, with hybrid epitaxial integration and SiGe channel engineering accounting for the largest filing clusters in this dataset. Filing density peaked during 2022–2024 before extending into novel application domains through 2026.
FDSOI Patent Count by Technology Cluster — Dataset Snapshot
Hybrid epitaxial region integration is the most heavily patented sub-domain in this dataset with at least 10 distinct filings, followed by SiGe channel and source/drain epitaxy, RF substrate engineering, back-gate architecture, and other process modules.
↗ Click bars to exploreFDSOI Filing Activity by Phase — Retrieved Records
Filing activity in this dataset peaked during 2022–2024 with the highest density of new patent families, representing the maturation and defect reduction phase, while 2025–2026 shows emerging entries into new application domains including image sensing and microfluidic thermal management.
↗ Click bars to exploreFDSOI Application Domains: RF, IoT, Radiation, and Imaging
Retrieved FDSOI patent records span six distinct application domains—from RF front-end modules and ultra-low-power IoT logic to radiation-hardened space electronics and CMOS image sensors—reflecting the platform’s versatility across both commercial and defense-grade requirements.
Mobile RF Front-End Modules
Skyworks Solutions holds a multi-jurisdictional patent family (US, GB, JP, SG — at least 5 records) covering FDSOI thin-film regions (5–50nm) for LNA and switch devices co-integrated with PDSOI thick-film regions (50–180nm) for power amplifiers on a single SOI die with insulator layer ≥100nm thick. IBM’s 2018 US patent further integrates ultra-low-power FDSOI digital logic with RF FETs and high-Q passives for mm-wave SoC designs targeting 5G/mmWave scenarios. CEA’s dual-compatible trap-rich SOI substrate enables both FDSOI digital and RFSOI passive functions on one wafer.
RF IntegrationUltra-Low-Power IoT Edge Nodes
Multiple records explicitly cite FDSOI’s 40% power savings vs. bulk CMOS at equivalent performance (Qinghe Crystal Element/Jincheng Semiconductor, 2023; Shanghai Goncheng Semiconductor, 2020–2021). Back-gate tuning, cited across at least 8 patents in this dataset, enables dynamic voltage/frequency scaling: forward back-bias boosts performance during active operation while reverse back-bias minimizes leakage during standby. A 2018 literature study on FDSOI 28nm for RF energy scavenging demonstrated 22% output voltage gain improvement over 350nm CMOS for rectifier circuits, directly supporting batteryless IoT applications.
Low-Power LogicRadiation-Hardened Space Electronics
Sun Yat-sen University filed a 2023 CN patent incorporating a hafnium oxide (HfO₂) ferroelectric layer and silicon nitride defect-trapping layer as the back-gate control stack to counteract threshold voltage drift induced by total ionizing dose (TID) effects. The HfO₂ ferroelectric layer amplifies the negative potential from radiation-trapped electrons in the SiN layer, providing self-compensating radiation hardening integrated directly into the back-gate stack without circuit-level modifications. Shanghai Huali’s 2024 TID-focused FDSOI device patent (CN) similarly targets reliability in radiation environments for satellite and defense electronics.
Radiation-HardenedFDSOI CMOS Image Sensor Platform
Shanghai Huali filed an FDSOI image sensor patent in March 2026 (CN), integrating FDSOI transistors including SiGe-channel PMOS variants within a CIS (CMOS Image Sensor) pixel architecture. Shallow STI is formed using a specialized oxide-as-stop-layer process adapted for the ultra-thin SOI geometry, avoiding conventional nitride-stop STI that would consume the already-thin SOI film. This filing represents the first extension of Shanghai Huali’s FDSOI platform from logic-only into mixed-signal and imaging applications within this dataset.
Image SensingLeading Patent Assignees in FDSOI — Dataset Snapshot
In this dataset of 74 retrieved records, filing activity is heavily concentrated among a small number of assignees. Shanghai Huali Integrated Circuit Corporation accounts for approximately 30 records in retrieved records, representing the largest single-assignee share by a substantial margin, while Reli Pingxin Microelectronics holds approximately 8 records in this dataset.
Top FDSOI Assignees by Filing Count in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreShanghai Huali Integrated Circuit Corp.
Shanghai Huali holds approximately 30 distinct patent records in this dataset, spanning CN and US jurisdictions with a filing history from 2018 to 2026 — the broadest date range of any single assignee in retrieved records. Technology coverage encompasses every major FDSOI process module: hybrid epitaxial region integration, SiGe channel engineering, STI formation, dummy gate removal, multi-layer source/drain epitaxy, image sensor integration, and TID radiation-hardening methods. Key 2026 US filings include a four-layer stacked S/D epitaxial structure preventing contact hole punch-through and an SiGe-channel PMOS CMOS image sensor platform with oxide-stop-layer shallow STI.
China — CN / United States — USReli Pingxin Microelectronics (Guangzhou)
Reli Pingxin Microelectronics holds approximately 8 records in this dataset with active filings from 2021 to 2026 in CN jurisdiction, covering back-bias chip architecture, epitaxial growth optimization, low-K spacer materials, and multi-Vt SiGe integration. The 2021 CN patent routes back-bias contacts through the wafer backside to reduce chip area overhead compared to conventional FDSOI designs, while the 2026 CN filing achieves multi-threshold-voltage integration by varying Ge concentration across regions of the same FDSOI die via differential Ge condensation without separate implant masking. Patent status includes both granted CN records and active applications through 2026.
China — CNFour Emerging FDSOI Innovation Vectors (2024–2026)
The most recent filings in this dataset (2024–2026) reveal four distinct vectors pushing FDSOI into new performance regimes and application domains: sub-14nm SiGe Ge condensation for PMOS performance parity, microfluidic thermal management for self-heating mitigation, FDSOI image sensor platform extension, and ferroelectric radiation-hardened back-gate engineering.
Sub-14nm SiGe Ge Condensation for PMOS Parity
Shanghai Huali’s 2025 CN filing discloses a Ge condensation process to form high-Ge-content SiGe channels within the SOI layer after gate oxide formation, with a silicon-rich surface passivation step to minimize interface state density. Reli Pingxin’s 2026 CN filing achieves multi-threshold-voltage integration by selectively varying Ge concentration across regions of the same FDSOI die without separate implant masking, realized via differential Ge condensation. Both filings represent a convergence of strain engineering and FDSOI back-gate architecture targeting NMOS/PMOS performance imbalance at 14nm and below.
Microfluidic Cooling for FDSOI Self-Heating Effect
The Institute of Microelectronics, Chinese Academy of Sciences, filed a patent in September 2025 (CN) integrating microfluidic cooling channels directly into the FDSOI device structure to address the self-heating effect (SHE) inherent to the low-thermal-conductivity BOX layer. This is the first and only thermal-management-specific FDSOI filing appearing in this dataset and signals emerging awareness of FDSOI thermal bottlenecks as a barrier to high-power-density applications. As FDSOI moves into RF PA integration and automotive MCUs, the thermally insulating BOX layer becomes a primary reliability concern.
FDSOI vs. FinFET: Architecture and IP Landscape Comparison
Click any row to explore further.
| Dimension | FDSOI | FinFET |
|---|---|---|
| Architecture | Planar trilayer: bulk Si handle, buried oxide (BOX), ultra-thin SOI top layer (6–20nm) | 3D vertical fin channel gated on three sides; no BOX layer |
| Channel Control | Full depletion of ultra-thin body; back-gate bias via BOX for dynamic Vt tuning | Electrostatic control via three-sided gate wrap; no back-gate tuning capability |
| Threshold Voltage Tuning | Back-gate bias through BOX layer; multi-Vt via SiGe Ge concentration variation (Reli Pingxin, 2026) | Fin width variation and threshold implant; less dynamic tuning flexibility |
| Power Efficiency | ~40% power savings vs. bulk CMOS cited in multiple retrieved records (Qinghe Crystal, 2023); forward/reverse body bias enables DVS | Superior leakage control at sub-10nm; higher dynamic power due to fin capacitance |
| RF Performance | BOX reduces parasitic junction capacitance; trap-rich HR substrate enables high-Q passives (CEA patents 2018–2021); FDSOI/PDSOI co-integration for RF FEM (Skyworks, 5–6 records) | Higher fin capacitance limits RF performance; less mature RF substrate ecosystem |
| Radiation Hardness | BOX-interface charge trapping under TID; addressed by HfO₂ ferroelectric back-gate (Sun Yat-sen, 2023) and anti-TID process (Shanghai Huali, 2024) | Better inherent TID tolerance in some implementations; no BOX charge trapping mechanism |
| Thermal Management | BOX has low thermal conductivity causing self-heating effect (SHE); microfluidic cooling patent filed by CAS (2025) — only 1 thermal-specific filing in dataset | Fin structure improves heat dissipation vs. planar; no BOX thermal barrier |
| Key IP Concentration | ~30 records from Shanghai Huali (CN/US) in this dataset; substrate IP at CEA/Soitec (FR) | Not covered in this dataset; patent landscape is separate |
Frequently Asked Questions: FDSOI Substrate Technology
FDSOI (Fully Depleted Silicon-On-Insulator) uses a trilayer stack — bulk silicon handle, buried oxide (BOX), and an ultra-thin SOI top layer (6–20nm) — enabling full channel depletion without doping. This eliminates random dopant fluctuation (RDF) effects that affect bulk CMOS, and improves threshold voltage stability. Unlike FinFET, FDSOI is a planar architecture that uniquely enables back-gate threshold voltage tuning via the BOX layer, offering dynamic voltage/frequency scaling not available in FinFET designs.
Shanghai Huali Integrated Circuit Corporation is the most prolific assignee in this dataset, with approximately 30 distinct patent records spanning CN and US jurisdictions, covering filings from 2018 to 2026. This portfolio covers virtually every major FDSOI process module including hybrid epitaxial region integration, SiGe channel engineering, STI formation, source/drain epitaxy, and image sensor integration.
The BOX layer in FDSOI functions as a second gate dielectric, enabling dynamic threshold voltage (Vt) tuning via a bias applied to the substrate below the BOX. Forward back-bias boosts performance during active operation, while reverse back-bias minimizes leakage during standby — a key requirement for IoT edge nodes. This back-gate tuning capability is a primary FDSOI competitive differentiator vs. FinFET and is cited across at least 8 patents in this dataset.
PMOS performance in FDSOI is constrained by low hole mobility in a pure silicon channel. SiGe channel integration introduces compressive strain to enhance hole mobility, but a secondary problem is germanium diffusion from the SiGe channel into the gate dielectric, which degrades reliability. Shanghai Huali’s 2022 US patents address this via a silicon cap layer preventing Ge diffusion and a nitrogen passivation layer providing both a Ge diffusion barrier and additional channel stress.
The most recent filings (2025–2026) in this dataset reveal four emerging vectors: (1) sub-14nm SiGe Ge condensation for PMOS performance parity at advanced nodes (Shanghai Huali, Reli Pingxin); (2) microfluidic cooling integration to address self-heating from the thermally insulating BOX layer (Institute of Microelectronics, CAS, 2025); (3) FDSOI image sensor platform extension with SiGe-channel PMOS within CIS pixel arrays (Shanghai Huali, 2026); and (4) ferroelectric radiation-hardened back-gate engineering using gadolinium-doped HfO₂ (Sun Yat-sen University, 2023).
Among retrieved records, CN dominates with approximately 40 filings, followed by US with approximately 25. Smaller clusters appear in GB (3 records), SG (3 records), EP (3 records), TW (2 records), JP (1 record), and DE (1 record). This pattern signals that China — led by Shanghai Huali — has become the most active jurisdiction for FDSOI process patent filing in this dataset, while US and European players dominate substrate supply, RF integration, and foundational architecture IP layers.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.