FinFET & GAA Transistor Patents: Who Leads, Where the Gaps Are 2026
- Filing has fallen sharply since its 2017 peak of 585 — by the most recent full year the count is down to single digits, consistent with the architecture's claim space having matured and consolidated rather than expanded.
- The United States receives the large majority of filings with 4,997 of the tracked records, dwarfing China's 286 and every other office — a strong signal of where litigation and licensing exposure concentrates.
- Momentum has gone quiet even among the largest holders with flagship assignees showing 0 or 1 filings in the latest year, which points to a technology being defended and licensed more than actively re-claimed.
Filing growth compares 2021 (303 records) with 2024 (114) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 6,302 records in scope (CR5), not by the ranked leaders only.
What the FinFET and GAA patent record actually shows
FinFET architecture moved transistor design from planar to three-dimensional gate control in order to suppress short-channel effects at shrinking nodes, and the patent record around it is now large and old enough to show a full lifecycle. The dataset covers 6,302 patent families filed against gate stack, fin patterning, threshold voltage and parasitic capacitance claims, spanning the shift from established FinFET structures toward gate-all-around and nanosheet transistor variants that extend the same channel-control logic vertically.
Filings peaked in 2017 at 585 and have declined every year since, with the 2022 midpoint sitting at 229 — a trajectory that looks like consolidation around a settled architecture rather than an emerging one. Readers should treat the most recent one or two years as understated: publication typically lags filing by around 18 months, so the near-zero counts shown for the latest year reflect a reporting gap as much as an actual filing pause.
Filing trend and technology composition
Two views of the same 6,302-family dataset: how filing volume has moved year over year, and how those families distribute across IPC subclasses covering semiconductor device structure, memory manufacture and digital processing.
A peak in 2017, then a steady decline
Filings ran at 585 in 2017 and had fallen to 7 by 2026 (a partial year), with the 2022 midpoint at 229 — a monotonic decline consistent with a technology whose core claim space filled early and has not reopened.
Concentrated in core semiconductor device classes
H01L accounts for 6,250 of the 6,302 records, effectively the whole dataset, with H10D (3,250), H10P (901) and H10B memory-device-manufacture claims (835) forming the largest sub-clusters; G11C, G06F and H10N appear only as smaller adjacent slices.
Shares are the percentage of the 6,302 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on FinFET and Gate-All-Around Transistor Architectures with Eureka
This page is one run against one query. Ask Eureka your own question about finfet and gate-all-around transistor architectures and every answer comes back with the patent numbers behind it.
Try EurekaThe patents everything else cites
Gate All Around Transistor Device and Fabrication Methods Thereof — TSMC, 2023-05-18
The filing claims a semiconductor device built from vertically stacked suspended nanostructures engaged by gate stacks with sidewall spacers, with a defined middle-portion thickness relative to a top surface — the core geometric setup used to describe nanosheet-style gate-all-around transistors.US20230155008A1, filed by Taiwan Semiconductor Manufacturing Co., Ltd.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6413802B1 | Finfet transistor structures having a double gate channel extending vertically from a substrate and methods o… | 1,387 |
| 2 | US9548303B2 | FinFET devices with unique fin shape and the fabrication thereof | 1,337 |
| 3 | US8860148B2 | Structure and method for FinFET integrated with capacitor | 1,330 |
| 4 | US8816444B2 | System and methods for converting planar design to FinFET design | 1,322 |
| 5 | US9214555B2 | Barrier layer for FinFET channels | 606 |
| 6 | US6642090B1 | Fin FET devices from bulk semiconductor and method for forming | 573 |
| 7 | US20160365414A1 | FINFET Structures and Methods of Forming the Same | 566 |
| 8 | US7101763B1 | Low capacitance junction-isolation for bulk FinFET technology | 564 |
| 9 | US20150091057A1 | Semiconductor structure and device and methods of forming same using selective epitaxial process | 546 |
| 10 | US9245805B2 | Germanium FinFETs with metal gates and stressors | 546 |
Citation counts inside this corpus skew toward older filings by construction — a high count signals influence on the field's early claim structure, not that the patent is still the one to watch.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Four figures from the dataset, and what each one means for a team deciding where to file, litigate or license next.
The core architecture is filed out, not emerging
A near-monotonic decline from 585 filings in 2017 to single digits by 2026 indicates the foundational FinFET claim space closed years ago. New entrants should expect dense prior art on the base structure and look instead to GAA and nanosheet refinements, where filing has not shown the same saturation.
Exposure sits overwhelmingly in the US
With receiving-office counts of 4,997 for the United States against 286 for China and 215 for the EPO, freedom-to-operate risk and licensing leverage are both concentrated in US filings far more than any other jurisdiction tracked here.
Even flagship holders have gone quiet
Assignees that historically anchored this space show at most one filing in the latest tracked year, with several logging a 100% year-over-year drop. That pattern is consistent with a portfolio being maintained and enforced rather than actively expanded.
Almost everything sits in one IPC family
H01L covers 6,250 of the 6,302 tracked families, with H10D, H10P and H10B forming the largest sub-clusters underneath it. The narrowness of the classification spread means differentiation between filers comes down to claim language within H01L, not which subclass they chose.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to finfet and gate-all-around transistor architectures, with the prior art for and against each one.
Assignees, collaboration patterns and where activity has slowed
The ranking itself is rendered separately; the pattern worth naming is concentration at the top alongside a long tail, and co-assignee links that trace specific R&D partnerships rather than broad industry alliances.
Internal entity pairs dominate co-filing
The strongest co-assignee link in the dataset — 97 shared families — sits between two SMIC entities (Shanghai and Beijing manufacturing arms), a pattern of intra-group co-filing rather than cross-company collaboration. The next-strongest pairs link IBM with GlobalFoundries (82) and IBM with STMicroelectronics Inc (41), reflecting the foundry-spinout relationships common in this space.
Only a handful of assignees still filing
In the most recent tracked year, IBM and Qualcomm each show a single filing, while TSMC, GlobalFoundries, Intel and SMIC Shanghai all show zero. TSMC's year-over-year change of -100% is the sharpest drop among historically active filers.
Collaboration is limited and specific
Only 10 co-assignee pairs appear across 6,302 families, and the strongest of them are internal-group or foundry-customer relationships rather than open consortia. That scarcity suggests most patent activity here is filed solo, by design teams protecting proprietary process integration.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 1 | -50% |
| Qualcomm Incorporated | 1 | — |
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 0 | -100% |
| GlobalFoundries | 0 | — |
| Intel Corporation | 0 | — |
| Semiconductor Manufacturing International (Shanghai) Corporation (SMIC Shanghai) | 0 | — |
| Samsung Electronics Co., Ltd. | 0 | — |
| Institute of Microelectronics, Chinese Academy of Sciences | 0 | — |
Where to take this analysis
The filing pattern here — a closed core, a quiet top tier, and a few specific under-claimed branches — points toward targeted rather than broad next steps.
Pressure-test a GAA or nanosheet claim draft
Run a specific claim on inner-spacer formation or nanosheet thickness gradients against the existing corpus before filing, since the core FinFET structure is saturated but these adjacent branches are not.
Draft and check claims in EurekaTrack the quiet top-tier holders
Zero or single-digit latest-year filings from historically dominant assignees can mean licensing activity is replacing new filing — worth monitoring rather than assuming disengagement.
Set up assignee monitoring in EurekaMap citation influence against current relevance
The most-cited records here date to the early FinFET era; before treating them as current freedom-to-operate risks, check filing and expiry status individually.
Explore citation trees in EurekaCommon questions about FinFET and GAA transistor patents
The 2017 peak of 585 filings in this dataset lines up with FinFET becoming the mainstream transistor architecture at leading nodes, which drew a wave of structural and process claims as manufacturers raced to cover fin patterning, gate stack and threshold voltage variations. Once the core geometry was well established and heavily claimed, the incentive to file incremental structural patents dropped, and attention shifted toward gate-all-around and nanosheet designs instead. The decline to single digits by 2026 should be read partly as a real slowdown and partly as an artefact of publication lag, since recent filings typically take about 18 months to appear in the record.
FinFET patents in this corpus generally claim a fin-shaped channel with the gate wrapped around three sides, while gate-all-around and nanosheet filings — like the representative TSMC filing in this dataset — claim vertically stacked suspended channel structures fully surrounded by the gate stack on all sides. Both fall under the same IPC subclasses (chiefly H01L and H10D) and address the same underlying problem of short-channel effects, but GAA claims tend to focus on stacking, inner-spacer formation and per-sheet work-function tuning rather than fin geometry. Because GAA is the newer branch, it shows less filing density than the core FinFET claim space, making it the more open area for new claim drafting.
The ranking is concentrated at the top among major foundries and integrated device manufacturers, with a long tail of single- or few-filing entrants below them. Co-assignee data shows the strongest internal filing links inside SMIC's Shanghai and Beijing manufacturing entities, alongside a notable IBM-GlobalFoundries collaboration reflecting their historical foundry relationship. However, latest-year filing counts for even the most prominent names have dropped to zero or one, so current filing leadership and historical citation leadership are not the same thing.
Given that H01L and its sub-classes account for nearly the entire dataset, differentiation now happens at the claim-language level rather than at the classification level. Specific branches — including nanosheet thickness gradient control, inner spacer formation between stacked channels, and source/drain epitaxy tailored to GAA junctions — show thinner claim density than core fin-patterning and gate-stack claims. These are the areas most likely to support a defensible new claim rather than one that collides with the saturated FinFET base layer.
Not necessarily. Publication lags actual filing by roughly 18 months in most jurisdictions, so the near-zero counts shown for the latest year understate real activity rather than proving it has stopped. What the data does show reliably is a multi-year decline from the 2017 peak and a shift in where filing volume sits — favouring adjacent GAA and nanosheet structures over further FinFET base claims. Anyone assessing current activity should treat the last one to two years of the trend as provisional and revisit it once later filings publish.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.