FinFET Chiplet / Standardized IP Patent Snapshot 2026
The current corpus for FinFET Chiplet / Standardized IP contains only 1 patent family in scope, filed in India in 2025, making meaningful competitive concentration analysis impossible at this stage. The evidence base is too limited to characterise dominant routes or pace of change; a broader search is strongly recommended before drawing R&D investment conclusions.
Corpus too thin for concentration analysis — single filing from India in 2025
The applicant ranking contains five co-filers, each holding 1 patent record, with DR SUNEEL KUMAR ASILETI listed as the top applicant. All five are individual inventors rather than established semiconductor corporations.
Because the top five filers account for the entirety of the ranked applicants visible in this query’ combined total, the apparent concentration figure of 100% reflects the extreme thinness of the corpus rather than a genuine oligopolistic structure.
| # | Applicant | Patent records | Share |
|---|---|---|---|
| 1 | DR SUNEEL KUMAR ASILETI | 1 | |
| 2 | TIRIVEEDHI RAVI CHANDH | 1 | |
| 3 | EAMANI RAMAKRISHNA REDDY | 1 | |
| 4 | DR BATTULA NANCHARAIAH | 1 | |
| 5 | KANAGALA SAI KRISHNA | 1 |
The single filing originates from India and was published in 2025. No inference can be drawn about leading positions among FinFET or chiplet industry participants — major industry actors such as TSMC, Intel, and Samsung do not appear in this corpus.
Results cover a 10-year global window through 2026; the 2025–2026 window is subject to publication lag and the 2025 record may not yet represent the full picture for that year. Longer-window growth, applicant concentration, and technology-route coverage are therefore more reliable signals than the latest-year bar alone.
Single 2025 filing; no multi-year trend or meaningful technology distribution
The annual filing trend shows zero activity from 2017 through 2024, with a single record appearing in 2025 and none yet in 2026. The technology composition spans four IPC classes, though the presence of B28D (working stone) alongside G06F and H04B raises a question about whether the filing’s classification fully captures FinFET chiplet subject matter.
Annual filing trend
The trend chart is flat at zero for the 2017–2024 window, with one record in 2025. This cannot be read as the start of a growth curve; it reflects the current state of the corpus and requires a wider search to validate. The 2025–2026 period is subject to publication lag.
↗ Hover for values · click a bar to ask EurekaTechnology composition
The four IPC classes — B28D (working stone), G06F (electric digital data processing), G06Q (business and administrative data processing), and H04B (transmission) — each carry a single record. The co-classification of B28D alongside G06F and H04B is atypical for semiconductor IP and may indicate a multi-invention filing rather than a focused chiplet patent portfolio.
↗ Hover for values · click a bar to ask EurekaHighly cited patent families surfaced by the query
Citation-heavy patent families returned by the query. Use this section as citation context, not as a curated list of the most topic-specific patents.
Design & analysis of a vedic mathematics based squ…
A novel method for squaring binary numbers using Vedic mathematics is proposed in this paper. The implementation of the binary squaring circuit uses the improved Vedic multiplier architecture. The circuit is designed in DSCH using the 14nm technology. Dwandwayoga has a duplex property that is used to find a square of an N-bit number. Also, Yavadunam is a… (excerpt from the patent abstract)
Open this patent in Eureka →Ranked by total forward citations. Citation counts favour older and broadly cited patent families, and broad or adjacent patents may appear when they match the search scope. Treat this section as citation context, not as a curated list of the most topic-specific patents. Some patent titles may be shown in their original, non-English language where an accurate translation could not be guaranteed.
Assignee snapshot from the current evidence set
The applicants below are visible in this query result. Because the evidence set is relatively small, read this section as a directional snapshot rather than a full competitive ranking.
DR SUNEEL KUMAR ASILETI
Listed as the top applicant with 1 patent record, shared with four co-inventors on the 2025 Indian filing. Technology focus spans B28D 5 (working stone), G06F 30, and G06F 7 (electric digital data processing). No momentum trend is available given the single record. This position reflects filing order rather than portfolio depth.
patent records: 1TIRIVEEDHI RAVI CHANDH
Holds 1 patent record as a co-inventor on the same 2025 Indian application. Technology classification mirrors that of the lead applicant: B28D 5, G06F 30, and G06F 7. No distinct trajectory can be established from a single shared filing. No momentum data is available.
patent records: 1Frequently asked questions
The current search returned 1 patent family in scope. This most likely reflects a narrow query definition rather than the true state of chiplet IP activity. Major players in FinFET and chiplet standardization hold substantial portfolios that would appear under broader search terms or alternative IPC classifications such as H01L.
The applicant ranking lists five individual inventors — DR SUNEEL KUMAR ASILETI, TIRIVEEDHI RAVI CHANDH, EAMANI RAMAKRISHNA REDDY, DR BATTULA NANCHARAIAH, and KANAGALA SAI KRISHNA — each holding 1 patent record as co-inventors on the same 2025 Indian application. No corporate entities appear in the current corpus.
The single record is classified under B28D (working stone), G06F (electric digital data processing), G06Q (business and administrative data processing), and H04B (transmission, general). The presence of B28D alongside semiconductor-adjacent classes is atypical and may reflect a broad multi-claim filing rather than a specialist chiplet patent.
India is the sole jurisdiction in the current corpus, with 1 patent record filed there. The United States, China, Taiwan, South Korea, and the European Patent Office — the primary jurisdictions for semiconductor IP — do not appear in the current results, which is a strong indicator that the search scope needs to be expanded.
The lifecycle stage is indeterminate from the current 1-family corpus; the evidence is insufficient to assign a stage. The broader industry context for chiplet standardization is one of active development, but this corpus cannot confirm that assessment.
No top-cited patents and no whitespace candidates were returned by the current analysis. Both require a sufficiently large corpus to generate meaningful citation networks and relative-density comparisons. An expanded search is needed to surface either.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.