FinFET Wafer Bonding / SOI Patent Landscape 2026
Taiwan Semiconductor Manufacturing Co. dominates a highly concentrated field, holding a commanding share of the top-ranked filers in FinFET wafer bonding and SOI technology. Annual filing volume has eased substantially from its 2018 peak, signaling a maturing, post-peak innovation cycle where incumbents defend established positions.
TSMC leads a sharply concentrated field of foundry and fabless incumbents
Taiwan Semiconductor Manufacturing Co. ranks first with 414 patent records, a gap that places it well ahead of every other applicant. International Business Machines Corporation follows at 100 patent records, and GlobalFoundries Inc. (combined entities) accounts for a further 134 patent records across its US and global registrations.
The top five filers account for 82% of the combined total of the hundred largest filers, indicating a tight oligopoly. A clear tier gap separates the top three from the remaining applicants, most of whom hold fewer than 20 patent records each.
| # | Applicant | Patent records | Share |
|---|---|---|---|
| 1 | Taiwan Semiconductor Manufacturing Co., Ltd. | 414 | |
| 2 | International Business Machines Corporation | 100 | |
| 3 | GlobalFoundries US Inc. | 89 | |
| 4 | Adeia Semiconductor Solutions LLC | 54 | |
| 5 | GlobalFoundries Inc. | 45 | |
| 6 | Semiconductor Manufacturing International (Shanghai) Corporation | 20 | |
| 7 | Parabellum Strategic Opportunities Fund LLC | 15 | |
| 8 | Institute of Microelectronics, Chinese Academy of Sciences | 15 | |
| 9 | Elpis Technologies Inc. | 14 | |
| 10 | Alsephina Innovations Inc. | 14 |
| # | Applicant | Patent records | Share |
|---|---|---|---|
| 11 | Qualcomm Incorporated | 9 | |
| 12 | Renesas Electronics Corporation | 8 | |
| 13 | Semiconductor Manufacturing International (Beijing) Corporation | 7 | |
| 14 | Texas Instruments Incorporated | 7 | |
| 15 | STMicroelectronics Inc. | 6 | |
| 16 | Applied Materials Inc. | 5 | |
| 17 | Avago Technologies International Sales Pte. Ltd. | 4 | |
| 18 | United Microelectronics Corporation | 4 | |
| 19 | Intel Mobile Communications GmbH | 4 | |
| 20 | Samsung Electronics Co., Ltd. | 4 |
The concentration of IP in the hands of leading foundries — TSMC, IBM, and GlobalFoundries — reflects the capital-intensive, process-IP-driven nature of FinFET and SOI development. New entrants face a dense prior-art landscape and strong portfolio barriers across the dominant H01L semiconductor device classes.
The most recent 18–24 months of filing data are subject to publication lag and will undercount true activity; late-period figures should be treated as provisional. Longer-window growth, applicant concentration, and technology-route coverage are therefore more reliable signals than the latest-year bar alone.
Filing volume peaked in 2018 and has since declined; semiconductor device classes dominate the technology mix
The annual filing trend reveals a field that crested in 2018 and has contracted on a multi-year basis, while the technology composition shows that semiconductor device fabrication (H01L) remains the overwhelmingly dominant branch, with smaller adjacent classes representing potential entry points.
Annual filing trend
Annual filings climbed from 85 in 2017 to a peak of 108 in 2018, then declined progressively through 2023–2024. The 2025–2026 figures reflect publication lag and should not be read as representing the full true activity for those years. The broader trend confirms that the field is contracting from its 2018 high.
↗ Hover for values · click a bar to ask EurekaTechnology composition
H01L (Semiconductor devices) and H10D (Semiconductor devices, general) together account for the large majority of IPC assignments, confirming that core device fabrication drives the corpus. H10B (Memory device manufacture), H10P, and H10W are present but at notably lower shares, pointing to adjacent sub-domains with relatively sparse coverage.
↗ Hover for values · click a bar to ask EurekaHighly cited patent families surfaced by the query
Citation-heavy patent families returned by the query. Use this section as citation context, not as a curated list of the most topic-specific patents.
Nanosheet (NS) and fin field-effect transistor (fi…
Certain aspects of the present disclosure are directed to a semiconductor device. The semiconductor device generally includes a substrate, at least one silicon-on-insulator (SOI) transistor disposed above the substrate, a gate-all-around (GAA) transistor disposed above the substrate, and a fin field-effect transistor (FinFET) disposed above the substrate. (excerpt from the patent abstract)
| # | Patent | Citations |
|---|---|---|
| 1 | Methods for fabricating finfet integrated circuits… | 242 |
| 2 | FinFET device and method of manufacturing same | 199 |
| 3 | Methods of forming single and double diffusion bre… | 160 |
| 4 | Bulk finfet with punchthrough stopper region and m… | 135 |
| 5 | Selective fin-shaping process using plasma doping … | 109 |
| 6 | Finfet with post-RMG gate cut | 107 |
| 7 | Methods for silicon recess structures in a substra… | 105 |
| 8 | Method and structure to create multiple device wid… | 102 |
Ranked by total forward citations. Citation counts favour older and broadly cited patent families, and broad or adjacent patents may appear when they match the search scope. Treat this section as citation context, not as a curated list of the most topic-specific patents. Some patent titles may be shown in their original, non-English language where an accurate translation could not be guaranteed.
What the patent structure means for R&D investment decisions
The combination of post-peak filing volume, extreme applicant concentration, and an active co-development ecosystem among foundry partners shapes the strategic context for any new entrant or incumbent considering further investment in FinFET wafer bonding and SOI.
Post-peak: foundational IP is largely established
The lifecycle stage is Decline, with annual filings easing back from the 2018 peak. Core FinFET and SOI process patents have been filed by leading foundries, suggesting that incremental process improvements are the more likely source of new filings rather than foundational architecture claims. New entrants should assess freedom-to-operate carefully against the dense incumbent portfolios.
Decline stageOligopoly structure limits competitive maneuvering
The top five filers hold 82% of the combined total of the hundred largest filers, with TSMC alone at 414 patent records. The tier gap between the top three and the rest is substantial. Mid-tier applicants such as Adeia Semiconductor Solutions LLC (54 patent records) and SMIC Shanghai (20 patent records) occupy niche positions well behind the leaders. Challengers must identify claim gaps rather than compete head-on in the dominant H01L sub-classes.
High concentrationIBM–GlobalFoundries consortium is the most active co-development axis
The most frequent co-filing pair is IBM and GlobalFoundries, with 17 jointly filed records, reflecting their historical foundry partnership on advanced node development. SMIC Shanghai and SMIC Beijing co-filed 7 records, indicating coordinated domestic Chinese development. IBM also co-filed with STMicroelectronics (6 records) and Renesas Electronics (5 records), while GlobalFoundries co-filed with both Renesas (5) and the French Atomic Energy Commission CEA (2), signaling a broader European research alliance.
Consortium activityUS filings dominate; China and Taiwan are secondary but active
The United States accounts for 726 patent records, firmly establishing it as the primary jurisdiction for this technology. China follows at 41 and Taiwan at 24, reflecting the geographic home bases of SMIC and TSMC respectively. Germany (18 records) likely corresponds to GlobalFoundries’ Dresden operations. PCT and EPO filings are sparse (3 and 4 records respectively), suggesting limited multi-jurisdictional prosecution strategies outside the US.
US-centricGo beyond the landscape: Eureka’s TRIZ Solution agent breaks down an R&D problem and returns patented concept solutions, each with a technical approach and cited patent & literature evidence.
| Applicant | Collaborator | Co-filings |
|---|---|---|
| International Business Machines Corporation | GlobalFoundries Inc. | 17 |
| Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor Manufacturing International (Beijing) Corporation | 7 |
| International Business Machines Corporation | STMicroelectronics Inc. | 6 |
| GlobalFoundries Inc. | GlobalFoundries US Inc. | 6 |
| International Business Machines Corporation | Renesas Electronics Corporation | 5 |
| GlobalFoundries Inc. | Renesas Electronics Corporation | 5 |
| GlobalFoundries Inc. | French Alternative Energies and Atomic Energy Commission (CEA) | 2 |
| GlobalFoundries Inc. | STMicroelectronics Inc. | 2 |
| STMicroelectronics Inc. | French Alternative Energies and Atomic Energy Commission (CEA) | 2 |
Co-filing pairs, ranked by the number of jointly-filed patent families.
TSMC commands the field; IBM and GlobalFoundries form a consortium-linked second tier
The top two players — Taiwan Semiconductor Manufacturing Co. and International Business Machines Corporation — differ in trajectory and route emphasis, with TSMC showing a declining recent trend while IBM anchors a co-development network that spans multiple foundry and IDM partners.
Taiwan Semiconductor Manufacturing Co.
TSMC leads with 414 patent records, concentrated in H01L 21 (process), H01L 29 (device structure), and H01L 27 (integrated circuits). Recent filing momentum shows a 36% decline versus the prior period, consistent with the field-wide post-peak trend. The portfolio depth nonetheless represents a formidable freedom-to-operate barrier across all core FinFET and SOI process and device sub-classes.
patent records: 414International Business Machines Corporation
IBM ranks second with 100 patent records, spread across the same H01L 21, H01L 29, and H01L 27 sub-classes. IBM’s distinctive strength is its role as the hub of the field’s most active co-development network, co-filing with GlobalFoundries (17 records), STMicroelectronics (6 records), and Renesas Electronics (5 records). Momentum data is not separately reported for IBM in this evidence set; its collaborative posture suggests continued standards and licensing activity rather than volume-driven prosecution.
patent records: 100| Applicant | Recent (3 yrs) | Trend |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. | 71 | ▼ -36% |
| Texas Instruments Incorporated | 1 | ▲ new entrant |
Memory integration and novel device classes are under-served relative to core FinFET process IP
While H01L and H10D account for the dominant share of filings, four adjacent IPC branches show comparatively sparse coverage, representing observations of relative sparsity in the corpus that may merit further technical evaluation.
H10B · Memory device manufacture
H10B accounts for 72 patent records and 5% of IPC assignments — a low share for a branch directly relevant to embedded memory integration on FinFET and SOI substrates. As DRAM and NVM scaling increasingly relies on bonded-SOI substrates and fin-based cell architectures, the intersection of wafer-bonding process IP with memory-specific device claims appears sparsely filed. Entry here would require expertise bridging SOI substrate preparation and memory array process integration, which existing foundry players have developed but not extensively patented in this sub-class.
Search this in Eureka →H10N · Other electric solid-state devices
H10N holds only 13 patent records — 1% of IPC assignments — despite the relevance of solid-state sensor and thermoelectric device architectures to SOI-based MEMS and power management integration. The sparsity here could reflect that established players have not yet systematically applied FinFET wafer-bonding techniques to non-standard device classes such as piezoelectric or spintronic structures. Technically, SOI’s thin-film isolation properties are well-suited to these applications, and the low incumbent filing density suggests relatively open claim space for applicants with cross-domain competence.
Search this in Eureka →How leading applicants differ in their IPC sub-class emphasis
Route coverage across the main technology branches in the current evidence set.
| Player | H01L 21 · Semiconductor devices | H01L 29 · Semiconductor devices | H01L 27 · Semiconductor devices | H10D 84 · Semiconductor devices (general) | H10D 62 · Semiconductor devices (general) |
|---|---|---|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. | Strong · 423 | Strong · 353 | Strong · 230 | Moderate · 155 | Moderate · 140 |
| International Business Machines Corporation | Strong · 192 | Strong · 167 | Strong · 125 | Moderate · 56 | Moderate · 68 |
| GlobalFoundries Inc. | Strong · 105 | Strong · 83 | Moderate · 40 | Moderate · 34 | Moderate · 29 |
| Semiconductor Manufacturing International (Shanghai) Corporation | Strong · 20 | Strong · 16 | Moderate · 6 | Absent | Absent |
| Institute of Microelectronics, Chinese Academy of Sciences | Strong · 15 | Strong · 8 | Absent | Absent | Absent |
| STMicroelectronics Inc. | Strong · 8 | Strong · 8 | Strong · 6 | Absent | Absent |
Frequently asked questions
The corpus contains 435 patent families in scope. Applicant rankings within the analysis are expressed in patent records, which can exceed the family count because a single family may be assigned across multiple jurisdictions.
Taiwan Semiconductor Manufacturing Co. ranks first with 414 patent records, a position that reflects decades of proprietary process development in FinFET gate-last and SOI substrate integration.
Annual filings peaked at 108 in 2018 and have declined progressively since. The lifecycle stage is classified as Decline, with a multi-year growth rate of -42% from the recent window. The most recent 18–24 months remain subject to publication lag, so 2025–2026 figures are provisional.
The United States is the dominant filing jurisdiction with 726 patent records. China (41) and Taiwan (24) are secondary markets, followed by Germany (18), which likely reflects GlobalFoundries’ Dresden facility. PCT and EPO coverage is sparse at 3 and 4 records respectively.
IBM and GlobalFoundries are the most active co-filers with 17 jointly filed records. SMIC Shanghai and SMIC Beijing co-filed 7 records. IBM also collaborated with STMicroelectronics (6 records), Renesas Electronics (5 records), and GlobalFoundries co-filed with Renesas (5 records) and the French Atomic Energy Commission CEA (2 records).
H10N (Other electric solid-state devices) at 13 patent records and H10B (Memory device manufacture) at 72 patent records are the sparsest branches relative to their technical adjacency to FinFET and SOI processes. H10P and H10W also show lower filing density compared to the dominant H01L and H10D classes.
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Disclaimer. This page is generated from PatSnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
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