A forksheet transistor places n-type and p-type channels side by side, separated by a dielectric wall grown between them, which lets designers shrink the n-to-p spacing without touching gate length. A CFET (complementary FET) instead stacks the n-type transistor directly above or below the p-type transistor, cutting the logic cell height rather than its width. Both are responses to the same problem: standard cell area is running out of lateral room to shrink, so the industry is folding structures into the vertical dimension. In this dataset both approaches are tracked together because the same process constraints — self-aligned contacts, thermal budget, dielectric wall formation — govern whether either structure is manufacturable.

The ranking covers 21 companies across 190 records in scope, and it is heavily front-loaded: the leading assignee holds 47 records, more than three times the fifth-place company’s 13. The top five assignees together account for 81.1% of all 190 records, and the top ten account for 95.8%, leaving little filing activity outside the ranked leaders. That concentration includes device manufacturers, a research institute, and semiconductor equipment and lithography suppliers, reflecting that both the transistor structure and the tools to build it are being actively claimed.

Yes, through the most recent complete year: filings rose from 17 records in 2021 to 47 in 2024, a 176% increase, with 2024 standing as the peak year in the dataset so far. Counts for 2025 and 2026 appear lower, but that reflects publication lag — patent applications typically publish around 18 months after filing, so recent years are still filling in rather than showing a genuine slowdown. Any claim about a decline in this field should be checked against that lag before being taken at face value.