Forksheet & CFET Patents: Who Leads, Where the Gaps Are 2026
- Five companies hold 81.1% of the field. 154 of 190 records in scope sit with the top five assignees, leaving a long tail of single- and double-digit filers behind them.
- Filings grew 176% from 2021 to 2024. The count rose from 17 to 47 records a year over that span, with 2024 as the peak year so far before publication lag thins the later years.
- Stacked and self-aligned contact structures dominate the cited art. The most-cited record alone carries 94 citations, and self-aligned contact schemes for walled nanosheet and forksheet devices sit close behind.
Filing growth compares 2021 (17 records) with 2024 (47) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 190 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Forksheet and complementary FET (CFET) architectures are the next structural step past lateral gate-all-around nanosheets: forksheet devices use a dielectric wall to shrink n-to-p spacing, while CFET stacks n- and p-type transistors vertically to cut cell height. Both approaches exist to solve the same problem — logic cell area is running out of room to shrink laterally, so the industry is folding the transistor pair into the third dimension instead. This dataset tracks 190 published records at the intersection of these structures and the process constraints that make them buildable: self-aligned processing, thermal budget, and contact placement.
The records span filings from 2015 through the 2026 cut-off, concentrated heavily in the most recent five years as foundries and equipment makers moved from concept papers to structural claims. Because publication lags filing by roughly 18 months, the 2025 and 2026 counts in any trend chart understate actual filing activity for those years.
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Filing trends and technology composition
Two views of the same 190 records: how filing activity has moved year over year, and which IPC subclasses carry the claim density.
A sharp run-up through the peak year
Filings sat near zero through 2017 and climbed steadily to a peak of 47 records in 2024, a 176% increase from the 17 filed in 2021. Treat 2025 and 2026 as still filling in rather than as a slowdown.
Concentrated in core semiconductor-device classes
H01L and H10D between them touch most of the corpus — 65.8% and 49.5% of the 190 records respectively — with memory-oriented H10B and H10W classes forming a smaller but consistent secondary cluster. Because records carry multiple classes, these shares add up to more than 100%.
Shares are the percentage of the 190 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Forksheet and Complementary FET Architectures with Eureka
This page is one run against one query. Ask Eureka your own question about forksheet and complementary fet architectures and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited and most representative filings
Complementary field effect transistor structures and methods of fabricating the same
The disclosed technology generally relates to a complementary field effect transistor (CFET) structure. In one aspect, the CFET structure includes at least one CFET element having a first transistor structure, and a second transistor structure arranged above the first, which includes a source and/or drain structure. The CFET structure further includes a power rail arranged below the first transistor structure and a power routing line arranged above the second, electrically connected to the source and/or drain structure of the second transistor structure.Filed by IMEC VZW, published 2025-06-19 — illustrates the current claim style around buried power rails combined with vertically stacked CFET elements.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20210407999A1 | Stacked forksheet transistors | 94 |
| 2 | US20210193821A1 | Self-aligned contacts for walled nanosheet and forksheet field effect transistor devices | 26 |
| 3 | US20220102520A1 | Semiconductor structure and forming method for thereof | 19 |
| 4 | US5214298A | Complementary heterostructure field effect transistors | 18 |
| 5 | US20230090092A1 | CMOS architecture with thermally stable silicide gate workfunction metal | 14 |
| 6 | US20210183711A1 | Self-aligned contacts for nanosheet field effect transistor devices | 13 |
| 7 | US20230290862A1 | Nanosheet Transistors with Reduced Source/Drain Resistance and Associated Method of Manufacture | 12 |
| 8 | US20220093647A1 | Forksheet transistors with dielectric or conductive spine | 12 |
| 9 | US20240072047A1 | Stacked fork sheet devices | 11 |
| 10 | US20220328477A1 | Semiconductor device structure including forksheet transistors and methods of forming the same | 11 |
Citation counts favour older records within the searched corpus and are a signal of influence, not of current claim strength.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three read-throughs from the concentration, trend and citation data above.
The core structural claims are largely staked out
With 154 of 190 records sitting inside the top five assignees, the foundational forksheet and CFET structural claims — dielectric wall formation, basic stacking sequences, source/drain isolation — are already dense prior art. New entrants filing on the same base structures face a crowded field.
Activity accelerated sharply into the peak year
The jump from 17 to 47 records a year tracks the industry's move from GAA nanosheet production to CFET research ahead of expected volume manufacturing later this decade. Momentum by individual assignee is uneven — several leaders show flat or declining latest-year counts, consistent with publication lag rather than a real pullback.
Stacking and self-aligned contacts anchor the influential art
The single most-cited record concerns stacked forksheet transistors, and a closely-cited second record covers self-aligned contacts for walled nanosheet and forksheet devices. Both point to contact formation and vertical stacking as the technical bottlenecks other filers are building around.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to forksheet and complementary fet architectures, with the prior art for and against each one.
Who is filing, and where the gaps sit
The ranked leaders account for 95.8% of the 190 records; the remaining companies file in single digits, leaving specific structural sub-problems open.
One filer well ahead of the field
The leading assignee's count is more than triple the fifth-place company's 13 records, reflecting an early and sustained push into stacked-transistor structural claims rather than a single burst of filing.
Process and tooling firms sit alongside device makers
Equipment and lithography suppliers appear inside the top ten alongside the device manufacturers, indicating that thermal budget and self-aligned processing constraints are being claimed from both the device and the tool side.
Joint filings cluster around one research hub
A research institute recurs as a co-assignee alongside both a university partner and a device manufacturer, pointing to a shared pre-competitive research track feeding separate downstream filers.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 2 | -60% |
| Samsung Electronics Co., Ltd. | 0 | -100% |
| Interuniversity Microelectronics Centre (IMEC) | 0 | — |
| Intel Corp | 0 | -100% |
| International Business Machines Corporation (IBM) | 0 | — |
| Applied Materials, Inc. | 0 | -100% |
| Huawei Technologies Co., Ltd. | 0 | — |
| eMemory Technology Inc. | 0 | — |
Where to take this
Three directions for turning this landscape into a filing or freedom-to-operate decision.
Map claim boundaries on the top-cited records
Start with the stacked forksheet transistor record and the self-aligned contact record — together they anchor most of the citation graph and define where independent claims already sit.
Explore citation chains in EurekaTrack the under-claimed process branches
Buried power rail integration and backside contact routing show thinner coverage than the core structural claims — worth a focused search before committing engineering resources.
Run a white space search in EurekaWatch momentum shifts across the leaders
Several top assignees show flat or falling latest-year counts, which may reflect publication lag rather than a real slowdown — monitor the next two publication cycles before drawing conclusions.
Set up assignee alerts in EurekaCommon questions on forksheet and CFET patents
A forksheet transistor places n-type and p-type channels side by side, separated by a dielectric wall grown between them, which lets designers shrink the n-to-p spacing without touching gate length. A CFET (complementary FET) instead stacks the n-type transistor directly above or below the p-type transistor, cutting the logic cell height rather than its width. Both are responses to the same problem: standard cell area is running out of lateral room to shrink, so the industry is folding structures into the vertical dimension. In this dataset both approaches are tracked together because the same process constraints — self-aligned contacts, thermal budget, dielectric wall formation — govern whether either structure is manufacturable.
The ranking covers 21 companies across 190 records in scope, and it is heavily front-loaded: the leading assignee holds 47 records, more than three times the fifth-place company's 13. The top five assignees together account for 81.1% of all 190 records, and the top ten account for 95.8%, leaving little filing activity outside the ranked leaders. That concentration includes device manufacturers, a research institute, and semiconductor equipment and lithography suppliers, reflecting that both the transistor structure and the tools to build it are being actively claimed.
Yes, through the most recent complete year: filings rose from 17 records in 2021 to 47 in 2024, a 176% increase, with 2024 standing as the peak year in the dataset so far. Counts for 2025 and 2026 appear lower, but that reflects publication lag — patent applications typically publish around 18 months after filing, so recent years are still filling in rather than showing a genuine slowdown. Any claim about a decline in this field should be checked against that lag before being taken at face value.
Relative to the dense prior art around basic dielectric-wall and stacking structures, a few process-level branches show thinner coverage: buried power rail integration with CFET stacks, backside contact routing for stacked nanosheet cells, and thermal budget management for sequential n-over-p stacking. These sit adjacent to heavily claimed core structures rather than being entirely unclaimed, so a freedom-to-operate check against the top-cited records is still advisable before filing. Middle-dielectric-wall etch selectivity for forksheet pitch scaling is another area worth checking, since it recurs in claim language but with fewer independent filings than the base structural claims.
US20250204018A1, filed by IMEC VZW and published 2025-06-19, is the representative record for current CFET claim style: it combines a buried power rail below the lower transistor with a power routing line above the upper one, connected to its source/drain structure. It illustrates where claim drafting has moved beyond the basic stacked-transistor structure toward power delivery integration within the same vertical stack. Anyone drafting claims in this space should read it closely, since buried power rail integration is also one of the less densely claimed branches identified in this dataset.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.