FPGA Architecture Patents: Who Leads, Where the Gaps Are 2026
- 70.6% concentration. The top 5 assignees combined hold 231 of 327 records in scope — filing here means designing around an occupied core, not an open field.
- Filing has gone flat. Volume peaked at 31 records in 2022 and has not grown since; the most recent year is still undercounted due to publication lag.
- Claims cluster tight. H03K and G06F together sit on the large majority of records, while power, ciphering and general semiconductor classes remain comparatively thin.
What this patent set covers
This landscape covers 327 published records filed between 2015 and 2026 that combine field-programmable gate array and programmable logic device terminology with claim language on look-up-table and routing fabric, hardened DSP or memory blocks, partial reconfiguration, static leakage, or high-level synthesis flows. The scope is deliberately narrow: it is not general reconfigurable computing, but the specific architectural and flow claims that define how an FPGA is built and programmed. Patent families, not raw document counts, are the fairer unit for judging real filing activity, and the ranking here is built on families.
Most records route through the United States receiving office, with Europe, WIPO and China each contributing smaller but active shares. That distribution reflects where the core architecture IP was first established rather than where demand is growing fastest today.
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Filing trend and technology composition
Two views of the same 327 records: how filing volume has moved year over year, and which IPC subclasses the claims actually sit in.
Filing trend, 2017–2026
Filings rose from 13 in 2017 to a peak of 31 in 2022, then flattened. With 2022 as the midpoint of the visible trend, growth in this dataset reads as flat to declining rather than accelerating — the last one to two years are also understated because publication typically lags filing by about 18 months.
IPC subclass composition
H03K (pulse technique and logic circuits) and G06F (electric digital data processing) each cover roughly two-thirds of the 327 records, confirming this is fundamentally a logic-fabric and data-processing field. H04L, G11C, G01R, H01L, H10D and G09C each cover a single-digit-to-low-teens share, marking transmission, memory, measurement, device-level and ciphering claims as secondary but present. Because a record can carry multiple IPC classes, these shares add up to well over 100% and should be read individually, not summed.
Shares are the percentage of the 327 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on FPGA Architecture and Programmable Logic with Eureka
This page is one run against one query. Ask Eureka your own question about fpga architecture and programmable logic and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited prior art in this space
US20040113655A1 — Partial reconfiguration of a programmable logic device using an on-chip processor
A programmable logic device, such as a field programmable gate array, is partially reconfigured using a read-modify-write scheme controlled by a processor: a base configuration is loaded, a frame of configuration data is read back, a subset of that frame is modified, and the modified frame overwrites the original in the configuration memory array.Filed by Xilinx, this record anchors the partial-reconfiguration branch of the dataset and is a useful reference point for freedom-to-operate review in that area.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US5646545A | Time multiplexed programmable logic device | 478 |
| 2 | US5784636A | Reconfigurable computer architecture for use in signal processing applications | 440 |
| 3 | US6091263A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data… | 428 |
| 4 | US5761483A | Optimizing and operating a time multiplexed programmable logic device | 340 |
| 5 | US6107821A | On-chip logic analysis and method for using the same | 329 |
| 6 | US5737235A | FPGA with parallel and serial user interfaces | 325 |
| 7 | US6480954B2 | Method of time multiplexing a programmable logic device | 318 |
| 8 | US6255849B1 | On-chip self-modification for PLDs | 306 |
| 9 | US20020010853A1 | Method of time multiplexing a programmable logic device | 297 |
| 10 | US5629637A | Method of time multiplexing a programmable logic device | 295 |
Ranked by citation count within this searched corpus. Older records dominate this list by construction — citation counts accumulate over time, so treat this as a signal of influence on later filings, not a signal of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three read-throughs from the concentration, trend and citation data that matter more for strategy than the raw counts alone.
The core is occupied, not open
Five assignees combined account for 231 of the 327 records in scope. New entrants filing on look-up-table structure, routing fabric or reconfiguration flow are filing directly over ground the leading assignees have already claimed repeatedly, not into empty space.
Filing has plateaued
The trend rose from 13 records in 2017 to a peak of 31 in 2022 and has not exceeded that since. Recent-year momentum by the leading assignees shows no year-over-year growth in the latest tracked year, though the most recent one to two years are always undercounted by publication lag.
Logic fabric and data processing dominate
H03K and G06F between them cover the large majority of records, confirming that routing, look-up-table structure and digital data processing are the load-bearing claim areas. Ciphering (G09C, 2.1%) and general semiconductor device claims (H10D, 3.1%) are comparatively open by contrast.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fpga architecture and programmable logic, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| DRC COMPUTER CORP | CASSELMAN STEVEN | 4 |
| DRC COMPUTER CORP | SAMPLE STEPHEN | 2 |
Only two co-assignee pairs appear in the dataset, both centred on DRC Computer Corp with individual named inventors — a sign that most FPGA architecture IP here is filed by a single corporate assignee rather than through joint ventures or research partnerships.
Who holds the ranked positions
The ranking covers 64 companies counted by records, not a top-50 or top-100 cut. The leader holds 96 records against a fifth-place figure of 14 and a tenth-place figure of 4 — a steep drop-off that defines how contested the top of this field is.
One assignee sets the pace
The top-ranked assignee holds 96 of the 327 records in scope, nearly seven times the fifth-place figure of 14. That gap is the clearest evidence in this dataset that a single company's claim portfolio anchors the field.
A steep tail below the leaders
By the tenth ranked position, holdings have fallen to 4 records. The distance between the leader and the tenth position is far larger than the distance between the tenth position and the bottom of the ranked list, which is the signature of a field with a small controlling group and a long tail of narrower filers.
No leader is currently filing at pace
Recent-year momentum data shows the leading tracked assignees at zero new records in the latest year, including a -100% year-over-year figure for one. This is consistent with the flat trend since the 2022 peak rather than a sign any leader has exited the space outright.
| Assignee | Recent year | YoY |
|---|---|---|
| Xilinx, Inc. | 0 | — |
| Altera Corporation | 0 | -100% |
| Lattice Semiconductor Corporation | 0 | — |
| Intel Corporation | 0 | — |
| Liquid Instruments Pty Ltd | 0 | — |
| Telefonaktiebolaget LM Ericsson (publ) | 0 | — |
| DRC COMPUTER CORP | 0 | — |
| Nantero, Inc. | 0 | — |
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, licensing, or scoping a new filing.
Run a freedom-to-operate check against the leader
With one assignee holding 96 of 327 records, any new filing on look-up-table, routing fabric or reconfiguration claims should be checked against that portfolio first, before broader landscape work.
Explore claims in EurekaScope the thinner IPC classes before filing
G09C, H10D and H01L each cover a single-digit share of the 327 records. That is a starting signal for open claim language, not a guarantee, and needs claim-level verification.
Analyse white space in EurekaTrack the leading assignees for renewed activity
Recent-year momentum is flat across the top tracked assignees. A resumption of filing by any of them would be an early signal worth monitoring given the 2022 peak and subsequent plateau.
Set up monitoring in EurekaCommon questions about FPGA architecture patents
The ranked leader in this dataset holds 96 of the 327 records in scope, well ahead of the fifth-ranked assignee at 14 and the tenth-ranked assignee at 4. The top 5 assignees combined account for 70.6% of all 327 records, and the top 10 combined account for 80.7%. This means the field is heavily concentrated at the top, with a long tail of smaller filers holding the remaining share.
Filing volume rose from 13 records in 2017 to a peak of 31 in 2022, and has not exceeded that peak since. Read against the 2022 midpoint, the overall trend is flat to declining rather than accelerating. It is worth remembering that publication typically lags filing by about 18 months, so the most recent one to two years in any such dataset will always look thinner than they will eventually turn out to be.
H03K (pulse technique and logic circuits) and G06F (electric digital data processing) are the dominant classes, covering 67.3% and 64.8% of the 327 records respectively. Secondary classes include H04L (digital information transmission, 10.1%), G11C (static and digital memories, 8.9%) and G01R (electric and magnetic measurement, 8.0%), with H01L, H10D and G09C each covering a smaller share. Because records often carry multiple IPC classes, these percentages overlap and do not sum to 100%.
US20040113655A1, filed by Xilinx, claims a partial reconfiguration method for a programmable logic device that uses an on-chip processor to perform a read-modify-write cycle: loading a base configuration, reading back a frame of configuration data, modifying a subset of values in that frame, and overwriting the original frame with the modified one. It is a process-level claim on how reconfiguration is executed rather than a claim on FPGA fabric itself. Anyone building a partial-reconfiguration flow that follows this same read-modify-write pattern should review this filing's claims and prosecution history closely before finalising an implementation.
The thinner IPC classes in this dataset — G09C (ciphering, 2.1% of 327 records), H10D (general semiconductor devices, 3.1%) and H01L (semiconductor devices, 5.5%) — carry noticeably fewer records than the dominant H03K and G06F classes. That does not mean these areas are unclaimed, but it does mean claim density is lower and there is more room to differentiate. Static leakage power management and high-level synthesis claim flows are two areas worth deeper claim-level review given comparatively thin coverage relative to core routing and look-up-table claims.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.