FPGA Partial Reconfiguration Patents: Who Leads, Gaps 2026
- Concentrated at the top. the top five assignees hold 84.8% of all 33 records in scope, and the top ten account for 100.0% — this is a field with almost no unranked long tail.
- One filer dominates the count. the leading assignee alone holds 12 of the 33 records, more than the next four combined.
- Filing has cooled from its peak. activity peaked at 9 records in 2021 and had fallen to 3 by 2024, a complete three-year span down 67%.
Filing growth compares 2021 (9 records) with 2024 (3) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 33 records in scope (CR5), not by the ranked leaders only.
What the data covers
This landscape tracks 33 published patent records matching claims and descriptions around FPGA partial reconfiguration — reconfiguration time, bitstream size, isolation between regions, resource fragmentation, safety during reconfiguration, and tool flow support. The scope spans filings from 2015 through the 2026 data cut-off, though publication lag means the most recent one to two years are still filling in.
Filings cluster in pulse-technique and logic-circuit classifications alongside general digital data processing, with smaller pockets touching AI-model computing, video and image processing, and semiconductor device structure. The receiving-office split is heavily weighted toward the United States, with a smaller but active presence at the EPO.
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Filing trend and technology composition
Two views of the same 33 records: how filing activity moved year over year, and which IPC subclasses carry the claims.
Filing trend, 2017–2026
Filings ran from 7 in 2017 to a peak of 9 in 2021, then declined to 3 by 2024 — a complete three-year span, down 67%. 2025 and 2026 figures are still incomplete because publication trails filing by roughly 18 months, so the apparent tail-off should not be read as the field going quiet.
IPC subclass composition
H03K (pulse technique and logic circuits) and G06F (electric digital data processing) each cover more than half of all 33 records, at 57.6% and 54.5% respectively — expected overlap, since most partial-reconfiguration claims touch both circuit-level logic and the data-processing flow that manages it. Smaller shares sit in AI-model computing and pictorial communication (12.1% each), data recognition (9.1%), semiconductor devices (6.1%), and single-digit pockets in electrography and general transmission.
Shares are the percentage of the 33 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on FPGA Partial Reconfiguration with Eureka
This page is one run against one query. Ask Eureka your own question about fpga partial reconfiguration and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in this space
Method and apparatus for partial reconfiguration circuit design for a programmable device (US7640527B1)
Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.Filed by Xilinx; granted 2009-12-29. One of the five most-cited records in this dataset.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6091263A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data… | 428 |
| 2 | US6150839A | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data… | 194 |
| 3 | US7224184B1 | High bandwidth reconfigurable on-chip network for reconfigurable systems | 102 |
| 4 | US6046603A | Method and apparatus for controlling the partial reconfiguration of a field programmable gate array | 95 |
| 5 | US7640527B1 | Method and apparatus for partial reconfiguration circuit design for a programmable device | 87 |
| 6 | US7482836B2 | High bandwidth reconfigurable on-chip network for reconfigurable systems | 77 |
| 7 | US20070200594A1 | High bandwidth reconfigurable on-chip network for reconfigurable systems | 37 |
| 8 | US10298356B1 | Optimal partial reconfiguration of spectrum in optical networks | 19 |
| 9 | US20210013885A1 | Logic fabric based on microsector infrastructure | 10 |
| 10 | US20210011636A1 | Logic fabric based on microsector infrastructure with data register having scan registers | 8 |
Citation counts favour older filings simply because they have had longer to accumulate references — treat this as a measure of influence on later work, not of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Beyond raw filing counts, citation weight and co-inventor patterns point to which technical threads have shaped the field and which teams worked closely together.
Early multi-region architecture claims still anchor the field
The most-cited record in scope, US6091263A, describes a multiple-region FPGA architecture with reconfiguration caches usable as data RAM — a structural idea that four of the five most-cited records in this dataset build on or reference directly.
Almost all activity sits with a small set of assignees
The top five assignees account for 84.8% of the 33 records in scope, and the top ten reach 100.0% — there is effectively no unranked long tail of single-filer entrants in this data.
A small, tightly linked inventor group drove several filings
Co-assignee data shows six pairings in total, with one inventor appearing in the three strongest pairs — a sign that a handful of individuals, rather than a broad internal team, carried a meaningful share of one assignee's output.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to fpga partial reconfiguration, with the prior art for and against each one.
Who holds the claim space, and where it thins out
Filing activity in FPGA partial reconfiguration sits with a small set of assignees, most of them established semiconductor and imaging firms, with a few academic entrants appearing lower in the ranking.
One assignee holds more than a third of the field
The top-ranked assignee alone accounts for 12 of the 33 records in scope — more than the next four assignees combined, and more than a third of everything filed in this space.
No ranked assignee shows fresh activity in the latest complete year
None of the leading assignees, including the top filer, show new records in the most recent year tracked — consistent with the broader trend decline from 9 filings in 2021 to 3 in 2024, though publication lag means this understates true recent activity.
Academic entrants appear only at the bottom of the ranking
Several university-affiliated applicants sit at the lower end of the 14-company ranking, each with a small number of records — a pattern consistent with academic groups publishing individual proof-of-concept work rather than building a filing programme.
| Assignee | Recent year | YoY |
|---|---|---|
| Intel Corporation | 0 | — |
| Xilinx Inc. | 0 | — |
| Omron Corporation | 0 | — |
| Fujitsu Ltd. | 0 | — |
| Fujifilm Business Innovation Corp. | 0 | — |
| LE THIEN | 0 | — |
| JANGITY ARUN | 0 | — |
| CHONG SIMON | 0 | — |
Where to take this from here
The dataset points to a concentrated field with a cooling but not dead filing trend. The next steps depend on whether you are scoping freedom-to-operate or looking for where to file.
Check freedom-to-operate against the top filer's portfolio
With one assignee holding 12 of 33 records, any new filing in core partial-reconfiguration mechanics should be checked against that portfolio specifically, not just the field average.
Explore assignee portfolios in EurekaMap the under-claimed sub-areas before drafting
Isolation, fragmentation-aware placement, and runtime safety checks show thinner coverage than core reconfiguration-time and bitstream-size claims — worth a closer look before committing claim language.
Run a white-space search in EurekaRe-run the trend once 2025–2026 data settles
The apparent decline from 2021's peak partly reflects publication lag; revisit filing-trend conclusions once those years are past their 18-month lag window.
Track filing trends in EurekaCommon questions about FPGA partial reconfiguration patents
This landscape covers 33 published patent records matching partial reconfiguration claims and descriptions, spanning filings from 2015 through the 2026 data cut-off. The ranking behind these records covers 14 assignees in total, so this is a comparatively small, concentrated field rather than a sprawling one. Because publication lags filing by roughly 18 months, the true count for the most recent one to two filing years will be higher than currently shown.
Filing activity is concentrated: the top five assignees together hold 84.8% of all 33 records in scope, and the top ten account for 100.0% of the field. The single leading assignee holds 12 records on its own, more than the next four ranked assignees combined. A handful of university-affiliated applicants appear near the bottom of the ranking with a single record each, suggesting isolated research output rather than sustained filing programmes.
Filings peaked at 9 records in 2021 and fell to 3 by 2024, a complete three-year span representing a 67% decline. That said, publication typically lags actual filing by around 18 months, so 2025 and 2026 figures in any dataset will look artificially low and should not yet be read as a continued decline. A fair read of momentum should wait until those years clear the lag window.
US7640527B1, held by Xilinx and granted in 2009, covers a method and apparatus for partial reconfiguration circuit design that floorplans static and reconfigurable logic together, runs design rule checks, and manages the resulting partial reconfiguration implementation. It sits among the five most-cited records in this dataset, indicating it has shaped a meaningful share of later filings. Anyone drafting claims around floorplanning-integrated partial reconfiguration tool flows should review it directly rather than relying on this summary alone, since citation weight signals influence, not the precise scope of its granted claims.
The IPC composition shows heavy concentration in pulse-technique circuits (57.6% of the 33 records) and general digital data processing (54.5%), with much thinner coverage in AI-model computing and pictorial communication (12.1% each) and semiconductor device structure (6.1%). Specific under-claimed threads include isolation guarantees between reconfigured regions, fragmentation-aware placement of partial bitstreams, and runtime safety checks during active reconfiguration. These are areas where claim density is lower, not areas confirmed to be technically easy — a search against the specific IPC classes is still warranted before drafting.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.