GAA DTCO / ML Patent Snapshot 2026
The intersection of Gate-All-Around transistor design, design-technology co-optimization (DTCO), and machine learning is an early-stage but rapidly expanding field, with Intel Corporation and Samsung Electronics jointly leading a highly concentrated corpus. Activity surged to a peak in 2023 and the field continues to expand on a multi-year basis, with the most recent years understated by publication lag.
Intel and Samsung share the lead in a tightly concentrated emerging field
Intel Corporation and Samsung Electronics Co. Ltd. each hold 3 patent families, placing them joint-first in the applicant ranking, with Synopsys Inc. third at 2 patent families. The top five filers collectively account for the entire output of the ranked applicants visible in this query in this corpus.
With only three identifiable applicants, the field exhibits extreme concentration — a hallmark of a nascent technology domain where foundational positions are still being staked. The gap between the top tier and any fourth-place entrant is, by definition, total: no other applicant has yet appeared in the ranked corpus.
| # | Applicant | Patent families | Share |
|---|---|---|---|
| 1 | Intel Corporation | 3 | |
| 2 | Samsung Electronics Co. Ltd. | 3 | |
| 3 | Synopsys Inc. | 2 |
Intel’s and Samsung’s parallel leadership signals that both integrated device manufacturers are treating GAA DTCO combined with ML-driven optimization as a strategic priority for sub-3 nm node development, while Synopsys’s presence confirms that EDA toolchain providers are also active in securing IP in this intersection.
The most recent filing years are further understated by standard patent publication lag; the true activity level in 2024 and beyond is likely higher than current counts suggest. Longer-window growth, applicant concentration, and technology-route coverage are therefore more reliable signals than the latest-year bar alone.
A 2023 surge anchors multi-year growth; semiconductor device IP dominates the technology mix
Two charts together reveal when activity accelerated and which technical branches attracted the most filings, giving a read on both the pace of innovation and its current focus.
Annual filing trend
Filings were negligible before 2019, rose modestly to 2022, then spiked sharply in 2023 — the peak year — before falling back in 2024. The 2024 and later years are understated by publication lag and should not be read as a real decline. The field is still expanding on a multi-year basis, with recent three-year filings well above the prior three-year window.
↗ Hover for values · click a bar to ask EurekaTechnology composition
H01L (Semiconductor devices) is the overwhelmingly visible IPC branch, reflecting the device-level focus of GAA and DTCO work. H10P and B82Y (Nanotechnology applications) appear as secondary branches, consistent with nanosheet transistor and nanowire architectures central to GAA structures.
↗ Hover for values · click a bar to ask EurekaHighly cited patent families surfaced by the query
Citation-heavy patent families returned by the query. Use this section as citation context, not as a curated list of the most topic-specific patents.
Integrated gate-all-around (GAA)/finfet transistor…
In embodiments of the present disclosure, an integrated transistor device includes a gate-all-around (GAA) transistor and a FinFET transistor device on the same substrate. The FinFET transistor includes a dielectric region between the channel of the FinFET transistor and the substrate. (excerpt from the patent abstract)
| # | Patent | Citations |
|---|---|---|
| 1 | Crystal orientation engineering to achieve consist… | 5 |
| 2 | Semiconductor device including nanosheet transistor | 3 |
| 3 | N-type transistor fabrication in complementary FET… | 3 |
Ranked by total forward citations. Citation counts favour older and broadly cited patent families, and broad or adjacent patents may appear when they match the search scope. Treat this section as citation context, not as a curated list of the most topic-specific patents. Some patent titles may be shown in their original, non-English language where an accurate translation could not be guaranteed.
Assignee snapshot from the current evidence set
The applicants below are visible in this query result. Because the evidence set is relatively small, read this section as a directional snapshot rather than a full competitive ranking.
Intel Corporation
Intel Corporation holds 3 patent families and is classified as a new entrant in the recent filing window, reflecting early but committed IP-building in GAA DTCO / ML. Its technology focus spans semiconductor device processing (H01L 21), device structure (H01L 29), and integrated circuit arrangements (H01L 27), indicating a broad-based approach covering fabrication process and device design together.
families: 3Samsung Electronics Co. Ltd.
Samsung Electronics Co. Ltd. also holds 3 patent families and similarly enters as a new entrant in the recent window, matching Intel’s count and trajectory. Its IPC focus mirrors Intel’s — H01L 29, H01L 21, and H01L 27 — suggesting both companies are competing on closely overlapping technical ground within GAA device architecture and DTCO-informed design.
families: 3Frequently asked questions
The current corpus stands at 8 patent families in scope. This is a small but meaningful dataset reflecting a nascent intersection technology that first saw activity around 2019 and peaked in 2023.
Intel Corporation and Samsung Electronics Co. Ltd. are joint leaders, each holding 3 patent families. Synopsys Inc. is third with 2 patent families. These three applicants account for the entirety of the ranked corpus.
The field is in a Growth lifecycle stage. Recent three-year filings are well above the prior three-year window, confirming multi-year expansion. Annual volume has eased from a 2023 peak, and the most recent years are further understated by publication lag, so the current pace of activity is likely higher than published counts indicate.
The United States leads with 5 patent records, followed by Europe (EPO) with 3. No other jurisdictions appear in the current evidence, which may reflect either early-stage geographic filing strategy or a genuine concentration of activity in these two markets.
The most-cited works in the corpus address crystal orientation engineering for consistent device behavior, nanosheet transistor architectures, and N-type transistor fabrication within complementary FET (CFET) structures — all foundational to GAA process and design-technology co-optimization.
No co-applicant filings are detected in the current corpus. All patent families are filed by single assignees. This absence of collaboration is consistent with the competitive sensitivity of leading-edge node IP among major integrated device manufacturers and EDA toolchain providers.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.