Book a demo

GAA Etching & Nanosheet Release Patent Landscape

GAA Etching & Nanosheet Release Patent Landscape
Competitive Landscape
GAA Etching & Nanosheet Release Patent Landscape in 2026

The GAA etching and nanosheet release space is highly concentrated, with TSMC and IBM together holding the majority of patent families among the top filers; annual filing volume peaked around 2018 and has eased substantially since, signaling a field moving through a mature, post-peak phase rather than an expanding frontier.

81
Patent families in scope
81%
Top-5 share of top-100 filers
-54%
3-yr filing growth (lag-adj.)
United States
Leading jurisdiction
↗ Tap any metric to explore the underlying patents and uncover deeper insights in PatSnap Eureka
Published byPatSnap Insights Team··6 min readVerified by PatSnap Eureka data
Overview

TSMC and IBM dominate a tightly consolidated field

Taiwan Semiconductor Manufacturing Co. Ltd. leads the ranking with 27 patent families, followed closely by International Business Machines Corporation at 21 patent families — the two together account for the majority share among the largest filers in this space.

The top five filers — TSMC, IBM, Applied Materials, Tokyo Electron, and Adeia Semiconductor Solutions — collectively hold 81% of the combined total across the hundred largest filers, indicating an exceptionally tight concentration with a steep drop-off to the next tier.

Leading applicants
#ApplicantPatent familiesShare
1Taiwan Semiconductor Manufacturing Co. Ltd.27
2International Business Machines Corporation21
3Applied Materials Inc.10
4Tokyo Electron Ltd.8
5Adeia Semiconductor Solutions LLC7
6GlobalFoundries US Inc.4
7Lam Research Corporation4
#ApplicantPatent familiesShare
8Tessera LLC2
9SMIC Manufacturing International (Beijing) Corp.2
10SMIC Manufacturing International (Shanghai) Corp.2
11SanDisk Technologies LLC1
12GlobalFoundries Inc.1
13French Alternative Energies and Atomic Energy Commission (CEA)1
↗ Hover a row · click a company to ask Eureka

Such concentration at the top implies that any new entrant or second-tier player faces strong prior-art density in core process and device architectures; differentiation will most plausibly come through adjacent process steps, equipment configurations, or non-standard channel materials rather than head-on competition in mainstream nanosheet release chemistry.

The most recent filing years are subject to publication lag and likely under-represent actual activity; conclusions about current competitive intensity should be read with that caveat. Longer-window growth, applicant concentration, and technology-route coverage are therefore more reliable signals than the latest-year bar alone.

Source: PatSnap Eureka. Chart shows the top applicants ranked by patent families. Applicant counts can overlap where a patent family lists several applicants, so they need not sum to the total in scope.Explore deeper in Eureka →
Trends & Structure

Filing activity peaked in 2018 and the technology mix is overwhelmingly semiconductor-device focused

The annual filing trend reveals a clear lifecycle arc, while the IPC composition confirms that the corpus is anchored in semiconductor device fabrication with only marginal coverage of adjacent disciplines.

Annual filing trend

Filings peaked at 14 patent families in 2018, declined through the early 2020s, and showed a partial uptick to 9 in 2024 before the most recent years taper off — the 2025 and 2026 data should be treated as incomplete due to publication lag, so the post-2023 trajectory is not yet determinative.

Annual filing trendAnnual values from 2017 to 2026, peaking at 14 in 2018.920171420181320191220201220214202242023920244202502026↗ Hover for values · click a bar to ask Eureka

Technology composition

H01L (Semiconductor devices) and H10D (Semiconductor devices, general) together dominate the IPC mix, confirming that filings are concentrated in core transistor fabrication; B82Y (Nanotechnology applications), H01J (Electron and discharge tubes), H10B (Memory device manufacture), and H10P each represent only single-digit shares, marking them as adjacent and relatively sparse branches.

Technology compositionH01L · Semiconductor devices leads with 89; H10D · Semiconductor devices (general) 55.H01L · Semiconductor dev…89H10D · Semiconductor dev…55B82Y · Nanotechnology ap…8H01J · Electron & discha…6H10B · Memory device man…6H10P6C23C · Coating & surface…2C30B · Crystal growth2↗ Hover for values · click a bar to ask Eureka
Source: PatSnap Eureka. Technology-branch counts are measured in patent records; a single patent family can carry several IPC classes, so class totals can exceed the family total in scope.Explore deeper in Eureka →
Key Patents

Highly cited patent families surfaced by the query

Citation-heavy patent families returned by the query. Use this section as citation context, not as a curated list of the most topic-specific patents.

Featured patent
US20190172751A1Published 2019-06-06

Method for controlling transistor delay of nanowir…

Tokyo Electron Limited

A method of manufacturing a semiconductor device includes: providing a substrate including a first stacked fin structure for forming a channel of a first gate-all-around (GAA) transistor, the first stacked fin structure including an initial volume of first channel material, and a second stacked fin structure for forming a channel of a second GAA transistor… (excerpt from the patent abstract)

Method for controlling transistor delay of nanowir… — patent drawingMethod for controlling transistor delay of nanowir… — patent drawing
Representative drawings from the patent document.
Open this patent in Eureka →
Highly cited patent families surfaced by this query
#PatentCitations
1Method for fabricating nanowires for horizontal ga…151
2Nanosheet transistor with improved inner spacer102
3Hybrid gate-all-around (GAA) field effect transist…92
4Method for incorporating multiple channel material…90
5Gate-All-Around (GAA) Method and Devices82
6Stacked Nanosheet CFET with Gate All Around Struct…72
7Multi-threshold voltage gate-all-around transistors72
8Method of forming integrated circuit with gate-all…56

Ranked by total forward citations. Citation counts favour older and broadly cited patent families, and broad or adjacent patents may appear when they match the search scope. Treat this section as citation context, not as a curated list of the most topic-specific patents. Some patent titles may be shown in their original, non-English language where an accurate translation could not be guaranteed.

Source: PatSnap Eureka. Citation-ranked patent families surfaced by this query.Open in Eureka →
Insights

What the structural data means for R&D investment decisions

Four dimensions — maturity, concentration, collaboration, and geography — together define the strategic constraints and openings for teams evaluating entry or expansion in GAA etching and nanosheet release.

Decline

Post-peak: core process IP is largely established

The lifecycle stage is Decline, with annual filings having eased back from the 2018 peak and a recent-window growth rate of –54%. The foundational process and device claims filed by the leading players are now well into prosecution or grant, meaning the freedom-to-operate landscape for latecomers is increasingly constrained in mainstream nanosheet release approaches. R&D investment is most defensible in differentiated sub-processes not yet densely claimed.

Lifecycle: Decline
Concentration

Top five hold 81% of the largest-filer pool

TSMC and IBM occupy the first two positions by a wide margin, with Applied Materials, Tokyo Electron, and Adeia Semiconductor Solutions forming a distant second tier. The sharp tier gap between the top two and the rest means that competitive parity through volume filing is not a realistic short-term strategy for new entrants. Targeted prosecution in under-claimed branches offers a more achievable differentiation path.

High concentration
Collaboration

Limited co-filing activity; SMIC entities and IBM-CEA are the only visible pairs

The collaboration evidence shows two co-filing relationships: SMIC Manufacturing International (Beijing) and SMIC Manufacturing International (Shanghai) filed jointly on 2 patent families, and IBM co-filed once with the French Alternative Energies and Atomic Energy Commission (CEA). The overall volume of collaborative filings is low relative to the corpus size, suggesting this space has developed primarily through internal R&D programs rather than industry consortia or academic partnerships.

Sparse collaboration
Geography

United States is the near-exclusive filing jurisdiction

The United States accounts for 87 patent records, with Taiwan and WIPO (PCT) each registering only 1 record. This heavy US concentration means the existing prior-art landscape is predominantly shaped by USPTO prosecution history and claim practice. Teams planning international commercialization should assess whether key process claims have been nationalized in other major semiconductor jurisdictions, as the evidence suggests limited direct protection in those markets from this corpus.

US-centric
PatSnap Eureka · TRIZ Solution Agent
Facing a specific technical bottleneck in this field?

Go beyond the landscape: Eureka’s TRIZ Solution agent breaks down an R&D problem and returns patented concept solutions, each with a technical approach and cited patent & literature evidence.

Solve it in Eureka →
Top collaboration links
ApplicantCollaboratorCo-filings
SMIC Manufacturing International (Beijing) Corp.SMIC Manufacturing International (Shanghai) Corp.2
International Business Machines CorporationFrench Alternative Energies and Atomic Energy Commission (CEA)1

Co-filing pairs, ranked by the number of jointly-filed patent families.

Source: PatSnap Eureka. Cards are grounded in applicant ranking, lifecycle, collaboration, and jurisdiction evidence from PatSnap Eureka.Explore insights →
Leaders

TSMC leads on volume; IBM matches on device architecture depth; equipment makers occupy a distinct tier

The top two players share a near-identical IPC focus but differ in trajectory, while Applied Materials and Tokyo Electron represent a separate equipment-process cluster below them.

Leader · TSMC

Taiwan Semiconductor Manufacturing Co. Ltd.

TSMC leads with 27 patent families concentrated in H01L 21 (semiconductor device manufacturing processes), H01L 29 (semiconductor device structures), and H10D 64 (general semiconductor devices). Recent filing momentum shows a modest decline of 7% versus the prior period, consistent with the field’s overall post-peak trajectory rather than any loss of strategic interest — TSMC’s position as the leading logic foundry makes sustained prosecution in this space commercially necessary.

families: 27
Challenger · IBM

International Business Machines Corporation

IBM holds 21 patent families with an IPC focus virtually identical to TSMC — H01L 21, H01L 29, and H10D 62 — reflecting deep engagement across both process and device structure dimensions. IBM’s co-filing with CEA on one family signals selective academic partnership activity. No momentum trend is separately evidenced for IBM in the applicant momentum data, but its volume and citation footprint (including the most-cited work on nanowire fabrication methods) position it as the strongest research-origin challenger to TSMC’s foundry-driven leadership.

families: 21
🔍
See the full applicant breakdown
Unlock rankings for all 13 identified applicants including equipment makers, IP holding companies, and emerging Chinese foundries.
Applied Materials Inc.Tokyo Electron Ltd.+ more
Unlock full assignee analysis →
Leading-applicant momentum (recent 3 yrs, lag-adjusted)
ApplicantRecent (3 yrs)Trend
Taiwan Semiconductor Manufacturing Co. Ltd.13▼ -7%
Applied Materials Inc.2▲ new entrant
Source: PatSnap Eureka. Patent family counts and technology focus are drawn from the applicant ranking and IPC focus evidence.Explore players →
Adjacent Branches

Under-served branches adjacent to the dominant semiconductor device core

Several IPC branches appear in the corpus at low counts and low share, indicating areas where patent density is sparse relative to the core H01L and H10D domains; these are observations of relative sparsity and should be evaluated on their own technical and commercial merits before being treated as entry opportunities.

H10B · Memory device manufacture

H10B covers memory device fabrication and appears in only 6 patent records at a 3% share — notably sparse given that GAA and nanosheet architectures are actively being explored for SRAM and emerging memory applications at advanced nodes. The technical relevance is plausible: nanosheet release processes developed for logic transistors are transferable to memory cell integration, and the low claim density suggests this intersection has not been systematically prosecuted. Teams with both logic-process and memory-integration expertise could find defensible ground here.

Search this in Eureka →

C23C · Coating & surface deposition

C23C (coating and surface deposition) appears in only 2 patent records at a 1% share, making it the sparsest adjacent branch in the corpus. Selective etch and release processes for nanosheets depend critically on surface passivation, atomic-layer deposition, and controlled deposition chemistries — all of which fall within C23C scope. The near-absence of filings here may reflect a tendency to classify this work under H01L rather than C23C, but it also leaves potential room for applicants whose core competency is deposition-side process chemistry rather than device architecture.

Search this in Eureka →
🔒
Unlock the full white-space map
See all five identified adjacent branches with share data and suggested search strings for deeper analysis.
B82Y · Nanotechnology applicationsH01J · Electron & discharge tubes+ more
Unlock full analysis →
Source: PatSnap Eureka. Branch sparsity is measured by patent-record count relative to the dominant H01L branch.Explore emerging →
Route Matrix

How leading applicants differ across technology routes

Route coverage across the main technology branches in the current evidence set.

PlayerH01L 21 · Semiconductor devicesH01L 29 · Semiconductor devicesH10D 62 · Semiconductor devices (general)H10D 64 · Semiconductor devices (general)H10D 30 · Semiconductor devices (general)
Taiwan Semiconductor Manufacturing Co. Ltd.Strong · 27Strong · 26Strong · 21Strong · 23Strong · 18
International Business Machines CorporationStrong · 24Strong · 24Strong · 16Strong · 16Strong · 14
Applied Materials Inc.Strong · 10Moderate · 4Moderate · 4Emerging · 1Moderate · 4
GlobalFoundries Inc.Strong · 5Strong · 5Strong · 4Strong · 4Moderate · 2
Tessera LLCStrong · 4Strong · 4Strong · 4Strong · 4Strong · 4
Tokyo Electron Ltd.Strong · 8Strong · 6AbsentAbsentAbsent
Lam Research CorporationStrong · 4Strong · 4AbsentAbsentAbsent
Source: PatSnap Eureka. Matrix values are measured in patent records and should not be compared directly with family-level applicant totals.Compare in Eureka →
Frequently asked questions

Frequently asked questions

Still have questions? PatSnap Eureka answers them from patent and research data.Ask Eureka →
PatSnap Eureka

Ready to map your own GAA nanosheet landscape?

Join 18,000+ innovators using PatSnap Eureka to map any technology landscape: search 2B+ patents and papers, surface key assignees, and generate a report like this in minutes.

18,000+innovators worldwide
2B+patents & papers
< 5 minper landscape report

Disclaimer. This page is generated from PatSnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.

Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.

Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. PatSnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.

Explore in Eureka ↗
Powered by PatSnap Eureka

Help us improve this page

Found incorrect or outdated information? Let us know and we'll get it fixed.