GAA Nanosheet Transistor Stacking — PatSnap Eureka
GAA Nanosheet Transistor Stacking: Architecture & Drive Current
Gate-all-around (GAA) nanosheet stacking is the leading transistor architecture at the 3 nm node and beyond — vertically multiplying channel width without expanding layout area. Explore the patent landscape, fabrication approaches, and drive current physics behind this breakthrough, powered by PatSnap Eureka.
What Is GAA Nanosheet Stacking and How Does It Work?
In a conventional FinFET, the gate electrode wraps around three sides of a vertical semiconductor fin, providing better electrostatic control than a planar transistor but still leaving one surface — the bottom — uncontrolled. GAA nanosheet transistors eliminate this limitation by suspending thin, flat sheets of semiconductor material — typically silicon or silicon-germanium — horizontally between source and drain regions, with the gate dielectric and gate metal completely encircling each sheet on all four sides.
As described in Samsung Electronics' 2022 patent on GAA nanosheet FETs, this "unitary gate material completely surrounding the horizontal nanosheet conductive channel structure" delivers electrostatic control from every direction, suppressing short-channel effects that plague scaled FinFETs. The PatSnap Analytics platform tracks this entire patent family across jurisdictions.
Stacking extends this principle into the vertical dimension. Rather than a single suspended nanosheet, multiple sheets are fabricated one above another — separated by sacrificial layers that are selectively etched away during processing — so that a single gate structure encloses an entire vertical array of channels. The Korea Nano Technology Institute's 2025 patent describes exactly this flow: a "multi-nanosheet structure on a substrate in which a selective sacrificial layer and a unit channel nanosheet are alternately stacked," followed by selective etching of the sacrificial layers to release the channel nanosheets, then formation of an all-around gate layer on the resulting multi-channel nanosheet structure.
The geometry of each individual nanosheet within the stack also matters. KAIST's 2023 patent demonstrates that both low-aspect-ratio and high-aspect-ratio nanosheet geometries can be employed within a GAA structure, noting that "compared to a conventional two-dimensional planar transistor, a higher driving current can be obtained, the short-channel effect can be suppressed more efficiently, and superior electrical characteristics can be exhibited per unit planar area." For semiconductor-focused R&D teams, PatSnap's materials science intelligence covers channel material innovations including SiGe variants.
How Vertical Stacking Multiplies Drive Current
Each additional nanosheet contributes an independent parallel current path under a shared gate — a direct, additive multiplication of effective channel width without consuming additional layout area.
Current Sums Across All Stacked Channels
The Chinese Academy of Sciences Institute of Microelectronics (2022) articulates this explicitly: the stacked nanosheet design with its "adjustable effective gate width and vertical stacking design in the horizontal direction can significantly enhance the current drive performance of the device." Since all channels share the same gate, source, and drain terminals, their individual currents sum directly — each additional sheet directly multiplying the total effective gate width and thus the on-state drive current.
No additional layout area requiredAll-Around Control Suppresses Short-Channel Effects
The all-around gate configuration eliminates the uncontrolled bottom surface of FinFETs. KAIST's 2023 patent confirms that this architecture "can suppress the short-channel effect more efficiently" even as gate lengths scale below 10 nm. Every nanosheet face enclosed by gate metal improves electrostatic integrity, enabling continued scaling that would be impossible with three-sided FinFET control. This is why WIPO patent filings in this domain have accelerated sharply since 2020.
Gate lengths scalable below 10 nmSource/Drain Resistance Becomes the Critical Bottleneck
Pohang University of Science and Technology's 2024 patent identifies parasitic source/drain resistance as a critical limiter of the drive current benefit and proposes extended source/drain regions that contact the stacked channels more effectively. As more nanosheets are added to the stack, ensuring adequate current injection at each sheet level becomes increasingly important. Qualcomm's Enhanced Geometric Extension Region patent (KR, 2026) similarly targets extension region geometry to reduce series resistance between channels and source/drain contacts.
Extended S/D regions address thisNanosheet Count Is the Primary Design Knob
Qualcomm's 2024 Variable Vertical-Stack Nanosheet patent makes the design tradeoff explicit: while more nanosheets increase drive current, fewer nanosheets reduce cell-level capacitance and lower power consumption. The filing proposes N nanosheets for high-performance cells and N−M nanosheets for low-power cells on the same wafer, providing "a novel way to drive the design to lower power through both reduced cell level capacitance as well as reduced" sheet count. Learn how PatSnap customers use this IP intelligence for chip design decisions.
N vs N−M sheets: perf vs. powerGAA Nanosheet Innovation by Assignee and Technical Axis
Analysis of 20+ active patents filed across US, Korea, Japan, Europe, China, and WIPO reveals a concentrated innovation landscape with clear technical focus areas per assignee.
GAA Nanosheet Patent Filings by Assignee
Samsung Electronics leads the dataset with the broadest coverage across GAA nanosheet design, fabrication, and layout migration. Qualcomm focuses on system-level power-performance optimization.
Primary Innovation Vectors in GAA Nanosheet Patents
Vertical stacking for current multiplication and gate electrostatics engineering dominate the patent landscape, with strain engineering and 3D cFET integration emerging as secondary axes.
Structural Variants and Manufacturing Innovations
From non-uniform sacrificial layer etching to CNT-based stacking and 3D cFET integration, patent filings reveal a rich landscape of structural differentiation strategies.
Non-Uniform Sacrificial Layer for Controlled Nanosheet Release
Samsung's 2021 patent addresses the precision SiGe removal step using a three-sub-layer sacrificial region with different etch rates — a fast-etching middle layer sandwiched between slower-etching upper and lower layers — to create self-limiting, well-controlled channel release. The precision of this SiGe removal step is a defining challenge in the canonical fabrication flow. The PatSnap Analytics platform tracks this patent family across all jurisdictions.
3-sub-layer SiGe sacrificial structureNon-Uniform Stack Geometry: Shorter Top Gate, Thinner Top Channel
Huawei's 2024 WO and EP patents propose a GAA nanosheet stack in which the topmost gate-metal layer has a shorter gate length than all lower gate-metal layers, with corresponding differences in channel layer thickness — inner channels at 3–6 nm, top channel at 2–5 nm — and spacer widths. This non-uniform stack geometry accommodates processing constraints at the top of the stack while maintaining electrical performance across all channel levels.
Inner: 3–6 nm · Top: 2–5 nm channelsKey Players and Their Strategic Focus Areas
A small number of companies account for the majority of substantive technical contributions, each with distinct innovation strategies across the GAA nanosheet design space.
Samsung Electronics — Broadest Design Space Coverage
Samsung is the most prolific assignee in the dataset, with patents covering basic nanosheet GAA structures, non-uniform sacrificial layer etching, horizontal nanosheet FETs, asymmetric gate-to-source/drain spacing, and layout migration tools from FinFET to nanowire/nanosheet geometries. Their 2022 Layout Design System patent enables FinFET layouts to be directly migrated to stacked nanowire designs by replacing fin-shaped pattern designs with wider nanowire structure designs — a critical design-technology co-optimization enabler.
Qualcomm — System-Level Power-Performance Flexibility
Qualcomm focuses on system-level design flexibility, with its variable nanosheet count family of patents (WO, US, IN — 2024–2025) targeting power-performance-area optimization by enabling different sheet counts in different logic regions on the same die. Qualcomm also addresses parasitic resistance through the Enhanced Geometric Extension Region patent (KR, 2026) and applies channel strain via inactive gate region strain materials (KR, 2026) — working for both NFET and PFET simultaneously by applying strain orthogonal to the channel direction.
Strain Engineering as a Complement to Geometric Stacking
Carrier mobility enhancement through strain is an additional route to drive current improvement in stacked nanosheet GAA devices, working independently of — and additively with — the geometric channel multiplication benefit. According to IEEE publications on strained semiconductor devices, strain-induced mobility gains can be substantial at nanoscale dimensions.
Qualcomm's GAA FET Strain Material patent (KR, 2026) describes incorporating strain-inducing materials in inactive gate regions "to apply channel strain to the channel(s) of the GAA FET to increase carrier mobility," working for both NFET and PFET simultaneously by applying strain orthogonal to the channel direction. This is notable because most strain engineering approaches favor either electron or hole transport — achieving simultaneous benefit for both device types is a key design challenge.
Intel's Strained Semiconductor on Insulator (SSOI) based GAA Transistor Structures patent (KR, 2023) describes GAA bodies — nanoribbons, nanosheets, or nanowires — placed under biaxial tensile strain via an underlying SSOI structure to boost carrier mobility independently of the geometric stacking benefit. The Korea Nano Technology Institute's 2022 patent further addresses the Si/SiGe intermixing problem that degrades interface characteristics when Si and SiGe are co-deposited, using lateral epitaxial growth for channel formation to avoid lattice constant mismatch effects that would otherwise degrade carrier transport in the stacked channels. PatSnap's life sciences and semiconductor teams both leverage this materials intelligence infrastructure.
Together, strain engineering and vertical stacking represent two orthogonal axes of drive current improvement: stacking multiplies the number of parallel channels, while strain increases the per-carrier velocity within each channel. NIST semiconductor metrology standards underpin the measurement frameworks used to validate both approaches.
Key Takeaways from the GAA Nanosheet Patent Landscape
Seven critical insights distilled from 20+ active patents spanning Samsung, Qualcomm, IBM, TSMC, Intel, Huawei, and leading research institutions.
Vertical Stacking Directly Multiplies Effective Channel Width
Each additional channel sheet contributes a parallel current path under a shared gate, without consuming additional layout area — a principle formalized in Samsung's nanosheet GAA FET architecture and elaborated in the CAS multi-threshold stacked nanosheet FET study.
Additive current per sheetAll-Around Configuration Eliminates FinFET's Uncontrolled Surface
The all-around configuration eliminates the uncontrolled bottom surface of FinFETs, suppressing short-channel effects even as gate lengths scale below 10 nm, as noted in KAIST's 2023 patent on planar and vertical nanosheet GAA MOSFETs.
4 controlled surfaces vs. 3Nanosheet Count Is the Primary Power-Performance Lever
Qualcomm's Variable Vertical-Stack Nanosheet patent demonstrates that providing N and N−M sheet counts on the same wafer enables flexible power-performance optimization across logic regions — more sheets for performance, fewer for low power.
N vs N−M sheets per logic regionSelective Sacrificial Layer Etching Is the Key Process Challenge
Samsung's non-uniform sacrificial region approach — using a three-sub-layer SiGe sacrificial structure with a faster-etching center layer — illustrates how controlled nanosheet release is engineered at the process level to avoid damaging the channel sheets during SiGe removal.
3-sub-layer SiGe etch controlReady to Run Your Own GAA Patent Analysis?
PatSnap Eureka gives R&D and IP teams AI-powered access to the full global GAA nanosheet patent database — search, cluster, and map claims in minutes.
GAA Nanosheet Transistor Stacking — key questions answered
GAA nanosheet transistors suspend thin, flat sheets of semiconductor material — typically silicon or silicon-germanium — horizontally between source and drain regions, with the gate dielectric and gate metal completely encircling each sheet on all four sides. This delivers electrostatic control from every direction, suppressing short-channel effects that plague scaled FinFETs.
The drive current improvement from nanosheet stacking is fundamentally additive: each additional nanosheet in the vertical stack contributes an independent conducting channel in parallel with all others. Since all channels share the same gate, source, and drain terminals, their currents sum directly. Industry practice typically targets three to four nanosheets per device in standard cell library implementations, with each additional sheet directly multiplying the total effective gate width — and thus the on-state drive current — without consuming additional layout area in the horizontal plane.
GAA nanosheet transistor technology has emerged as the leading candidate to replace FinFET architectures at the 3 nm process node and beyond. In a conventional FinFET, the gate electrode wraps around three sides of a vertical semiconductor fin, leaving one surface (the bottom) uncontrolled. GAA eliminates this limitation by surrounding each nanosheet channel on all four sides, delivering superior electrostatic control and suppressing short-channel effects even as gate lengths scale below 10 nm.
Selective sacrificial layer etching is the key manufacturing challenge. The canonical flow relies on depositing alternating Si (channel) and SiGe (sacrificial) epitaxial layers, then removing the SiGe layers via selective wet etching to release the nanosheets. Samsung Electronics addressed this with a non-uniform sacrificial layer approach using a three-sub-layer SiGe sacrificial structure with a faster-etching center layer to create self-limiting, well-controlled channel release.
Nanosheet count is the primary design knob for trading drive current against power and capacitance. While more nanosheets increase drive current, fewer nanosheets reduce cell-level capacitance and lower power consumption. Qualcomm's variable nanosheet count patent proposes N nanosheets for high-performance cells and N−M nanosheets for low-power cells on the same wafer, enabling flexible power-performance optimization across logic regions.
Strain engineering complements geometric stacking for carrier mobility enhancement. Qualcomm's GAA FET patent describes incorporating strain-inducing materials in inactive gate regions to apply channel strain to the channel(s) of the GAA FET to increase carrier mobility, working for both NFET and PFET simultaneously by applying strain orthogonal to the channel direction. Intel's SSOI-based GAA transistor structures describe GAA bodies placed under biaxial tensile strain via an underlying SSOI structure to boost carrier mobility independently of the geometric stacking benefit.
Still have questions? Let PatSnap Eureka answer them for you.
Ask Eureka About GAA TechnologyAccelerate Your GAA Nanosheet R&D with AI-Powered Patent Intelligence
Join 18,000+ innovators already using PatSnap Eureka to accelerate their R&D — search 20+ active GAA nanosheet patents from Samsung, Qualcomm, IBM, TSMC, Intel, Huawei, and more in one AI-powered workspace.
References
- Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architectures — Samsung Electronics Co., Ltd., 2022
- Manufacturing method of gate all-around device using multi-channel nanosheet — Korea Nano Technology Institute, 2025
- Manufacturing method of field effect transistor having vertically stacked nanowire channels using lateral epitaxy growth — Korea Nano Technology Institute, 2022
- Metal-oxide-semiconductor field effect transistor with planar or vertical nano-sheet channel wrapped by gate all around — Korea Advanced Institute of Science and Technology, 2023
- Multi-threshold stacked nanosheet GAA-FET device array and its manufacturing method — Chinese Academy of Sciences Institute of Microelectronics, 2022
- Variable vertical-stack nanosheet for gate-all-around devices — Qualcomm Incorporated, US, 2024
- Variable vertical-stack nanosheet for gate-all-around devices — Qualcomm Incorporated, WO, 2024
- Variable vertical-stack nanosheet for gate-all-around devices — Qualcomm Incorporated, IN, 2025
- GAA FET devices employing strain material in the inactive gate region(s) to apply channel strain for increased carrier mobility — Qualcomm Incorporated, KR, 2026
- Enhanced geometric extension region(s) for GAA FET devices — Qualcomm Incorporated, KR, 2026
- Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same — Samsung Electronics Co., Ltd., 2021
- Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same — Samsung Electronics Co., Ltd., 2021
- Methods of making nanosheet based devices — Huawei Technologies Co., Ltd., WO, 2024
- Methods of making nanosheet based devices — Huawei Technologies Co., Ltd., EP, 2024
- Self-aligned hybrid substrate stacked gate-all-around transistors — International Business Machines Corporation, WO, 2023
- Hybrid stacked field effect transistor — International Business Machines Corporation, JP, 2024
- Nanosheet transistors with asymmetric gate stacks — International Business Machines Corporation, KR, 2022
- Strained semiconductor on insulator (SSOI) based gate all around (GAA) transistor structures — Intel Corporation, KR, 2023
- Field-effect transistor and semiconductor device including the field-effect transistor — Samsung Electronics Co., Ltd., 2020
- Semiconductor device — Taiwan Semiconductor Manufacturing Company, Ltd., US, 2023
- Gate-all-around field-effect transistor with extended source/drain and manufacturing method thereof — Pohang University of Science and Technology, KR, 2024
- Layout design system, Semiconductor device and method for fabricating the same — Samsung Electronics Co., Ltd., 2022
- Semiconductor device comprising different gate structures and method for fabricating thereof — Samsung Electronics Co., Ltd., KR, 2025
- IEEE — Electron Devices Society publications on FinFET and GAA transistor scaling
- WIPO — International patent filings database for semiconductor device innovations
- NIST — Semiconductor metrology and measurement standards
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. Patent analysis covers 20+ active filings across US, Korea, Japan, Europe, China, and WIPO jurisdictions, filed between 2020 and 2026.
PatSnap Eureka searches patents and research to answer instantly.