GAA Wafer Bonding Patent Snapshot 2026
GAA wafer bonding is a concentrated, early-growth field dominated by Université Catholique de Louvain, with a small cluster of major semiconductor companies entering as new filers in the most recent cycle. Filing activity has accelerated sharply from a near-zero base, though the absolute corpus remains limited, leaving meaningful room for new entrants to establish position.
Université Catholique de Louvain leads a tightly held, nascent field
The patent evidence snapshot for GAA wafer bonding is highly concentrated: Université Catholique de Louvain sits at the top of the applicant ranking, followed by Intel Corporation and a set of individual inventors and large-cap semiconductor firms each holding a single patent record.
The top five filers collectively account for 76% of the combined total across the ranked applicants visible in this query, signalling a steep tier gap between the academic leader and the rest of the field. No commercial incumbent has yet assembled a portfolio of meaningful depth.
| # | Applicant | Patent records | Share |
|---|---|---|---|
| 1 | Université Catholique de Louvain | 7 | |
| 2 | Intel Corporation | 3 | |
| 3 | NEVE DE MEVERGNIES AMAURY | 1 | |
| 4 | IBM (International Business Machines Corporation) | 1 | |
| 5 | RASKINS JEAN PIERRE | 1 | |
| 6 | DE MEVERGNIES AMAURY NEVE | 1 | |
| 7 | Taiwan Semiconductor Manufacturing Co. (TSMC) | 1 | |
| 8 | Tokyo Electron Ltd. | 1 | |
| 9 | RASKIN JEAN PIERRE | 1 |
The leading position of an academic institution rather than a chip manufacturer suggests that foundational IP is still being established, and industrial players entering now — Intel, IBM, TSMC, and Tokyo Electron — are at an early stage of staking claims rather than defending mature positions.
Patent publication typically lags filing by 18–24 months, so the most recent period is likely under-represented in the current counts. Longer-window growth, applicant concentration, and technology-route coverage are therefore more reliable signals than the latest-year bar alone.
Filing activity is rising sharply from a near-zero base, concentrated in semiconductor device classes
Two charts below capture the pace of activity and the technology composition of the corpus. Together they show a field in early growth with a narrow but deepening IPC footprint.
Annual filing trend
Activity was negligible from 2017 through 2021, registered its first meaningful cluster in 2022, and showed the highest single-year count in 2024. The 400% recent-window growth figure reflects acceleration from a very small base. The 2025 and 2026 bars should be treated as understated owing to publication lag.
↗ Hover for values · click a bar to ask EurekaTechnology composition
The corpus is overwhelmingly concentrated in H01L (semiconductor devices), confirming that filings address core device fabrication and integration rather than peripheral process equipment or materials. A single record appears under H10D (semiconductor devices, general), representing an adjacent but sparsely populated branch.
↗ Hover for values · click a bar to ask EurekaHighly cited patent families surfaced by the query
Citation-heavy patent families returned by the query. Use this section as citation context, not as a curated list of the most topic-specific patents.
Self-aligned gate endcap (SAGE) architectures with…
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate… (excerpt from the patent abstract)
| # | Patent | Citations |
|---|---|---|
| 1 | Fabrication method of so1 semiconductor devices | 316 |
| 2 | Fabrication method of so1 semiconductor devices | 8 |
| 3 | 3D single crystal silicon transistor design integr… | 7 |
| 4 | Fabrication method of SOI semiconductor devices | 5 |
Ranked by total forward citations. Citation counts favour older and broadly cited patent families, and broad or adjacent patents may appear when they match the search scope. Treat this section as citation context, not as a curated list of the most topic-specific patents. Some patent titles may be shown in their original, non-English language where an accurate translation could not be guaranteed.
Assignee snapshot from the current evidence set
The applicants below are visible in this query result. Because the evidence set is relatively small, read this section as a directional snapshot rather than a full competitive ranking.
Université Catholique de Louvain
The institution holds 7 patent records — the largest portfolio in this corpus by a wide margin — focused entirely on H01L semiconductor device fabrication and transistor design. All co-filings involve individual researchers affiliated with the institution, indicating a faculty-led IP generation model. No momentum trend is reported for the leader, consistent with an established base position rather than a recent surge.
patent records: 7Intel Corporation
Intel holds 3 patent records and is classified as a new entrant with an upward momentum trend. Its technical focus spans H01L 21, H01L 27, and H01L 29 — covering semiconductor processing, integrated circuits, and transistor structures — signalling a broad-based rather than narrow entry into GAA wafer bonding IP. Given Intel’s scale and process-technology investment cycle, this new-entrant position could escalate rapidly.
patent records: 3Frequently asked questions
The current corpus contains 6 patent families in scope. This is a very small corpus consistent with an early-growth field where foundational IP is still being established.
Université Catholique de Louvain holds the most patent records in the corpus, followed by Intel Corporation. The remaining filers — including IBM, TSMC, and Tokyo Electron — each hold a single patent record.
The United States leads in patent-record count, followed by Europe via the EPO. Additional records appear in Australia, Germany, Austria, and one WIPO PCT filing, indicating limited but geographically spread international coverage.
The field is classified as Growth, with annual filings still rising. The most recent years are likely understated due to publication lag. The 400% recent-window growth rate reflects acceleration from a near-zero base rather than a mature high-volume field.
All identified co-applicant pairs involve Université Catholique de Louvain paired with individual researchers — Jean-Pierre Raskin, Amaury Neve de Mevergnies, and Denis Flandre. Industrial entrants have filed independently, suggesting industry–academia joint filing programs have not yet emerged in this area.
H01L (semiconductor devices) accounts for the overwhelming majority of patent records, covering device fabrication, integrated circuits, and transistor structures. A single record falls under H10D (semiconductor devices, general), filed by TSMC, making it the only adjacent branch currently represented.
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Disclaimer. This page is generated from PatSnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
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