GaN HEMT Packaging Patents: Who Leads, Where the Gaps Are 2026
- 34 families total a small, concentrated corpus where a handful of documents carry most of the citations.
- Filing peaked in 2023 at 12 and has not returned to that level since, with the midpoint year 2022 sitting at 9.
- One embedded-die filing dominates citations US20220020669A1 is cited 23 times, more than twice its nearest peer.
What this landscape covers
This landscape tracks patent activity at the intersection of GaN HEMT device design and advanced packaging — embedded die construction, low-inductance package architectures, and the printed-circuit and clip-based interconnects that let a gallium nitride power transistor actually deliver its switching speed in a finished module. The search combines device-level terms (GaN HEMT, GaN transistor) with packaging-specific terms (GaN power packaging, low-inductance package, embedded die packaging), so records that only describe bare die or only describe generic packaging without a GaN link are excluded.
Coverage runs from 2015 through the 2026-07-31 cut-off. Because publication typically lags filing by around 18 months, the last one to two years of the trend line will read lower than actual filing activity once those applications publish.
Filing trend and technology composition
The two views below show how activity has moved over time and where it sits across IPC subclasses — together they indicate whether this is a growing field or one that has already plateaued.
A flat-to-declining curve after a 2023 peak
Filings were at zero in 2017, rose to a midpoint of 9 by 2022, and peaked at 12 in 2023. There is no sustained climb beyond that peak, which is consistent with a niche packaging problem being addressed by a small set of specialists rather than an industry-wide land grab.
Concentrated in semiconductor device classes
H01L (semiconductor devices) accounts for 27 of the records and H10W for 22, with much smaller counts in H10D, H05K, H01Q and H10P. That concentration means most of the inventive activity is being claimed as device/package structure rather than as antenna integration or discrete circuit assembly, even though a few filings touch those adjacent areas.
Shares are the percentage of the 34 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Gallium Nitride HEMT Advanced Packaging with Eureka
This page is one run against one query. Ask Eureka your own question about gallium nitride hemt advanced packaging and every answer comes back with the patent numbers behind it.
Try EurekaThe documents carrying the most influence
Embedded die packaging for power semiconductor devices (US20220020669A1)
Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in a laminated body comprising a layer stack of dielectric and electrically conductive layers. Dielectric build-up layers of filled or fiber-reinforced material combine with copper interconnect and copper-filled vias; where a solder resist coating is used, a dielectric build-up layer sits between it and the underlying copper interconnect.Filed by GaN Systems Inc., published 2022-01-20 — the most-cited record in this corpus at 23 citations.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20220020669A1 | Embedded die packaging for power semiconductor devices | 23 |
| 2 | US20150041967A1 | Molded Semiconductor Package with Backside Die Metallization | 9 |
| 3 | US20200235067A1 | Electronic device flip chip package with exposed clip | 8 |
| 4 | US9099454B2 | Molded semiconductor package with backside die metallization | 8 |
| 5 | US11342248B2 | Embedded die packaging for power semiconductor devices | 6 |
| 6 | US11776883B2 | Embedded die packaging for power semiconductor devices | 4 |
| 7 | CN113937086A | 功率半导体器件的嵌入式裸片封装 | 4 |
| 8 | WO2024137283A1 | 3‑d IC in embedded die substrate | 3 |
| 9 | US20230282540A1 | Substrates for power stage assemblies comprising bottom-cooled semiconductor power switching devices | 2 |
| 10 | WO2020154364A1 | Electronic device FLIP chip package with exposed clip | 2 |
Citation counts are drawn from the searched corpus only and skew toward older filings that have simply had more time to accumulate citations.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Three patterns stand out once the trend, the IPC split and the citation table are read together.
One embedded-die family sets the reference point
US20220020669A1, and its related family member US11342248B2, describe embedding the power die directly in a laminated dielectric/copper stack. Their combined citation weight makes them the de facto reference architecture that later filers design around rather than ignore.
Activity has not grown past its 2023 peak
With the midpoint year at 9 and no year since exceeding 12, filing volume looks flat rather than accelerating. That is typical of a packaging sub-problem that a small group of specialists has largely mapped, rather than a land grab still in progress.
Claims sit overwhelmingly in device/package structure
H01L and H10W dominate the IPC split, while H05K (printed circuit assemblies), H01Q (antennas) and H10P register only a handful of records each. RF-antenna and PCB-assembly integration are present but thin, not absent.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gallium nitride hemt advanced packaging, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Texas Instruments Incorporated | Texas Instruments Japan Ltd. | 1 |
Only one co-assignee pairing appears in the corpus, Texas Instruments with its Japan subsidiary, filing together once. Most other assignees file independently rather than through joint development structures.
Who is filing, and where the claim space is still open
Recent-year momentum is muted across the board: every tracked assignee shows zero filings in the latest year, and one shows a full year-over-year drop from prior activity. That is consistent with the flat trend line rather than any single company pulling ahead now.
GaN Systems Inc.
Holds the most-cited record in the corpus, US20220020669A1, describing embedded die packaging in a laminated dielectric/copper stack for high-voltage, high-temperature operation. Its related family member US11342248B2 extends the same approach.
ON Semiconductor
Contributes molded package and backside die metallization art (US20150041967A1, US9099454B2) that predates the embedded-die wave and remains a citation anchor for later work.
Murata, Infineon, Pasernac, Texas Instruments
Each of these names appears in the assignee ranking but with no filings recorded in the most recent tracked year, matching the corpus-wide plateau rather than any single firm's retreat.
| Assignee | Recent year | YoY |
|---|---|---|
| GaN Systems Inc. | 0 | — |
| Murata Manufacturing Co., Ltd. | 0 | — |
| ON Semiconductor | 0 | -100% |
| Infineon Technologies AG | 0 | — |
| Pasernac Inc. | 0 | — |
| Texas Instruments Incorporated | 0 | — |
| Texas Instruments Japan Ltd. | 0 | — |
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, portfolio strategy, or identifying a filing gap.
Check freedom-to-operate against the embedded-die family
Any embedded-die or low-inductance package design should be checked claim-by-claim against US20220020669A1 and US11342248B2 before committing to a layout.
Run a claim comparison in EurekaWatch for publication-lag catch-up
The 2024–2026 filing counts will rise as pending applications publish; re-pull the trend in six to twelve months before concluding the field has cooled.
Set a monitoring alert in EurekaScope a filing in the thinner IPC branches
H05K, H01Q and H10P each carry only a handful of records, which may indicate genuine white space rather than mere disinterest — worth a targeted novelty search.
Explore white space in EurekaCommon questions about this landscape
GaN HEMT advanced packaging refers to the package-level structures — embedded die construction, low-inductance interconnect, clip or flip-chip attach — that let a gallium nitride high-electron-mobility transistor switch at high frequency without the package parasitics undoing the device's speed advantage. It needs separate claims from the transistor itself because the same GaN die can be packaged in molded, embedded, or flip-chip form, each with distinct thermal and inductance tradeoffs. Packaging claims typically cover the dielectric stack, interconnect geometry, or die-embedding process rather than the semiconductor structure, so a company can hold strong packaging IP even without owning core GaN device patents.
By citation count in this corpus, GaN Systems Inc. holds the most-cited record, US20220020669A1, describing a power die embedded in a laminated dielectric and copper-interconnect stack for high-voltage, high-temperature operation. ON Semiconductor's older molded-package and backside-metallization filings (US20150041967A1 and US9099454B2) also carry significant citation weight and predate the embedded-die approach. Citation counts favor older documents simply because they have had more time to be cited, so treat this as a measure of influence rather than current market share.
The filing trend in this dataset peaked at 12 filings in 2023 and has not exceeded that level since, with the 2022 midpoint at 9 filings. That pattern reads as flat to declining rather than accelerating. Recent years should be read cautiously, though, because publication typically lags filing by around 18 months, so the most recent one to two years in any patent trend will always look lower than the true filing rate once pending applications publish.
The IPC composition shows heavy concentration in H01L and H10W (semiconductor device and package structure), with only a handful of records in H05K (printed circuit assemblies), H01Q (antennas) and H10P. That thin coverage suggests under-claimed territory in areas like PCB-embedded GaN packaging and antenna-integrated modules combining HEMT die with RF front-end packaging. Anyone considering a filing there should still run a targeted novelty search, since a low count in this specific search string does not guarantee the space is unclaimed under a different keyword combination.
Rarely, based on this dataset. Only one co-assignee pairing appears across the 34 families — Texas Instruments filing jointly with its Japan-based subsidiary — and every other tracked assignee files independently. That suggests packaging IP in this niche is being developed and held internally rather than through joint ventures or cross-licensing structures, at least within the scope of this search.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.