T-gate patterning is the lithography step that defines a narrow gate foot for short channel length while keeping a wider gate head to reduce gate resistance, which matters directly for RF performance in GaN HEMTs. Because the geometry trade-off is process-specific rather than a property of the semiconductor material itself, patent offices treat the patterning method as a distinct invention from the device structure it produces. That is why this landscape searches gate lithography and T-gate patterning terms specifically, rather than relying on general GaN HEMT device claims, and why H01L filings dominate even though the underlying material science sits closer to crystal growth classes like C30B.

The corpus shows academic and state-research filers, including an MIT-affiliated inventor network and Singapore's national research agency, alongside established semiconductor and defense names such as Raytheon, Texas Instruments and Stanford's licensing office. None of these assignees show filings in the most recent tracked year, so recent momentum does not identify a current leader — cumulative family counts in the ranking table are the more reliable measure. Filing concentration by receiving office is also notable: the United States and Israel together account for most of the activity.

Yes, based on the data available: filings rose from 2 in 2017 to a peak of 17 in 2019, then fell back to 6 by the 2022 midpoint. That is a single wave rather than sustained growth. Remember that publication lags filing by roughly 18 months, so the very low 2025 and 2026 figures are partly a reporting artefact and should not be read as a sudden stop — but the multi-year plateau before that lag window is a genuine signal that the core patterning approaches for this generation of devices are largely staked out.

US20200083167A1 covers nitride structures with low-capacitance gate contacts integrated with copper damascene structures, and it is the most-cited record in this corpus at 33 citations, more than double the next-highest reference. Any team using damascene-style copper integration for the gate contact in a GaN HEMT process should review this claim set closely before finalizing a process flow, since it appears to anchor a meaningful share of the citing prior art in this field. Designing around it likely means either a different contact metallization sequence or a different capacitance-reduction mechanism than the damascene approach it claims.

The IPC composition shows thin coverage in a few specific branches: only 3 of 49 records touch C30B crystal growth, and only 2 each touch H02H protective circuits and H10P, despite the dense H01L coverage across the rest of the corpus. That suggests claim space combining gate-lithography methods with substrate-quality engineering, or with protective-circuit co-integration at the gate module level, is comparatively open. A first claim there would likely need to tie a specific gate-recess or T-gate step to a measurable substrate or protection-circuit outcome, rather than claiming the gate structure alone.