Dynamic on-resistance testing measures how a GaN HEMT's conduction resistance changes under switching conditions compared to its static, DC-measured value — a phenomenon often called current collapse. Because GaN devices can show a significantly higher on-resistance immediately after a high-voltage switching event than a static test would predict, dedicated dynamic test circuits are needed to characterise real-world efficiency and reliability. In this dataset, dynamic on-resistance test circuits are the single most cited category, with two Chinese filings, CN111337807A and CN102721913A, each carrying 15 citations. Anyone qualifying GaN devices for power applications typically needs this kind of test alongside standard static measurement.

This dataset contains 16 published patent families matching the combined search for GaN HEMT devices and dynamic on-resistance, wafer-level test, or reliability screening methods. That is a small, specialised pool compared to the broader GaN power device literature, reflecting that this search targets the test-methodology layer specifically rather than device fabrication as a whole. Filing activity peaked at 5 families in 2020 and has not shown a sustained increase since. Given an 18-month typical publication lag, the most recent one to two years in this count should be treated as incomplete rather than as evidence of a slowdown.

Filing in this space is spread across individual inventors, Chinese universities and a handful of semiconductor manufacturers, with no single dominant assignee across the 16 families. The strongest documented collaboration is between the named inventors Zhang Guobiao and Yu Peter Y, linked across 4 families. Academic filers such as the University of Electronic Science and Technology of China also appear, sometimes co-filing with affiliated research institutes. None of the named assignees show filings in the most recent year, which is consistent with the field's generally intermittent filing pattern rather than pointing to any one company withdrawing.

US20190198624A1, assigned to Hong Kong Haicun Technology, claims a GaN-on-Si output transistor array built from small monolithic transistor cells grown in individual grid segments, where defective cells are disabled to improve overall yield and reliability. This is a specific architectural approach to yield improvement through cell segmentation and selective disabling, not a claim over dynamic on-resistance testing or wafer-level screening methods generally. Work that improves yield through different means, such as process control, material quality improvements or post-fabrication trimming without a segmented-array structure, sits outside what this filing describes. Anyone considering a segmented small-cell GaN array architecture should review this filing's claims closely before proceeding.

Based on the IPC composition, most inventive activity concentrates in electrical measurement circuitry (G01R, 10 records) and semiconductor device structure (H01L and H10D, 7 and 6 records respectively), while materials analysis methods (G01N) appear in only 2 records. This suggests thinner direct coverage around areas like in-situ trap-state characterisation during dynamic testing, correlation of wafer-level burn-in data to field failure rates, and automated pass/fail thresholding for production screening lines. These are not confirmed gaps — they are areas where this dataset shows less density relative to the core test-circuit claims, and a proper freedom-to-operate search would be needed before relying on them as open space.