The corpus shows filing concentrated among a mix of device manufacturers and universities rather than a single dominant holder. The most-cited foundational records date back to the late 2000s and early 2010s and relate to integrated HEMT and lateral field-effect rectifier combinations, which still anchor much of the citation graph. Any clearance search should start with those records before moving to more recent, narrower integration filings such as the 2025 STMicroelectronics application.

Filing volume has declined from a 2018 peak of 16 families to roughly half that by 2022, and no tracked assignee shows growth into the latest year. That points to a maturing architecture rather than a shrinking market — the underlying GaN device business continues to grow, but the foundational structural claims were largely staked out by the late 2010s. New filings now tend to sit at the process-integration layer, such as combining normally-on and normally-off devices on one platform.

A normally-off HEMT is a device that does not conduct current with zero gate voltage, which matters for power-switching safety and is a key differentiator from the naturally depletion-mode behaviour of standard GaN HEMTs. Much of the p-GaN gate architecture patenting in this corpus exists specifically to achieve normally-off operation without sacrificing the high electron mobility that makes GaN attractive in the first place. Claims in this space typically cover the gate stack composition, threshold-voltage control method, or a specific fabrication step such as plasma treatment.

The United States accounts for 90 of the 148 tracked records, making it the primary jurisdiction for any clearance work, followed by Europe at 17 and the PCT route at 12. China, Germany and India each have a smaller but non-trivial presence in the single digits, so a global product launch still warrants a local check in those markets even though the bulk of the enforceable prior art sits in the US.

Cascode GaN structures pair a depletion-mode GaN HEMT with a low-voltage silicon FET to achieve normally-off behaviour at the circuit level, while p-GaN gate architecture achieves normally-off behaviour at the device level by altering the gate stack itself. Both routes are represented in this corpus and are frequently cited together in search strings because they solve the same normally-off requirement through different means. Patent claims tend to diverge sharply here: cascode claims often extend into H02M power-conversion and H03K logic-circuit territory, while p-GaN claims stay concentrated in H01L and H10D device-structure classes.