GaN HEMT Wafer Bonding Patents: Who Leads, Where the Gaps Are 2026
- Flat, not rising. Filings peaked at 10 in 2024 after sitting at 4 in 2022 — this is a mature, occupied niche rather than a growth curve.
- Citation weight sits in 2006-2008. The most-cited records (100 and 81 citations) predate the current filing wave by more than a decade, meaning newer entrants are building on old foundational claims.
- US-centric filing. Of the tracked receiving offices, the United States accounts for 25 of the filings tracked, roughly triple the next-largest office — Europe at 8.
What this landscape covers
This review covers patent families indexed under gallium nitride HEMT wafer bonding — filings that combine HEMT device claims with engineered-substrate or layer-transfer bonding techniques, drawn from title/abstract/claim searches across 2015 to 2026. The dataset spans 52 patent families and is concentrated almost entirely in semiconductor device classifications, with H01L capturing 50 of the 52 records.
Because publication lags filing by roughly 18 months, the 2025 and 2026 counts in the trend chart understate actual filing activity for those years; treat the most recent two data points as provisional rather than a genuine drop-off.
Filing trend and technology composition
Two views of the same 52-family dataset: how filing activity has moved year over year, and how those filings distribute across IPC subclasses.
A flat filing curve since the mid-2010s
Filings moved from 2 in 2017 to a midpoint of 4 in 2022, then peaked at 10 in 2024 before the partial, understated 2025-2026 figures. There is no sustained upward trajectory here — this reads as a technology with a stable population of repeat filers rather than a wave of new entrants.
Concentration in core device classes
H01L (semiconductor devices generally) covers 50 of 52 records, with H10D and H10W as the next-largest secondary classifications. The presence of H03K (pulse technique and logic circuits) and G09G (display control) at low single-digit counts marks where HEMT bonding work touches circuit-level and display applications, but these remain minor branches relative to the device-fabrication core.
Shares are the percentage of the 52 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Gallium Nitride HEMT Wafer Bonding with Eureka
This page is one run against one query. Ask Eureka your own question about gallium nitride hemt wafer bonding and every answer comes back with the patent numbers behind it.
Try EurekaThe records shaping this space
Transfer of wide and ultrawide bandgap layers to engineered substrate
Filed by the University of South Carolina, this record describes 193-nm excimer laser-based lift-off of AlGaN/GaN HEMTs built with thick AlN heat-spreading buffer layers grown on sapphire. The approach lowers thermal resistance from roughly 25-50 Kmm/W for standard sapphire-based HEMT structures down to 16 Kmm/W as-fabricated, and to 8 Kmm/W once the lifted-off device is soldered to a copper heat sink — a figure comparable to published results on bulk SiC substrates.Abstract condensed from the original filing.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20060284247A1 | Novel method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates | 100 |
| 2 | US20120319169A1 | CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof | 81 |
| 3 | US20170309676A1 | Engineered Substrate Including Light Emitting Diode and Power Circuitry | 78 |
| 4 | US7420226B2 | Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates | 28 |
| 5 | US20080296617A1 | METHOD USING LOW TEMPERATURE WAFER BONDING TO FABRICATE TRANSISTORS WITH HETEROJUNCTIONS OF Si(Ge) TO III-N M… | 23 |
| 6 | US20210151428A1 | Integration of heterogeneous transistors on diamond substrate by layer transfer | 20 |
| 7 | US20180219106A1 | Lateral gallium nitride jfet with controlled doping profile | 16 |
| 8 | US10290674B2 | Engineered substrate including light emitting diode and power circuitry | 11 |
| 9 | US9070758B2 | CMOS compatible method for manufacturing a HEMT device and the HEMT device thereof | 8 |
| 10 | WO2006138378A1 | Silicon CMOS and algan/GAN wideband amplifiers integrated on engineered substrates and method of manufacturin… | 8 |
Citation counts reflect influence within the searched corpus at the time of the search and favour older filings; they are not a measure of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Four read-outs from the filing trend, citation pattern and jurisdiction split, aimed at where to file and what to watch.
Growth, but not sustained
The rise from 4 families in 2022 to a peak of 10 in 2024 looks like acceleration, but with 2017 already at 2 and the trajectory otherwise flat through the midpoint, this is closer to periodic bursts of filing from a small set of repeat assignees than a structural upswing.
Foundational art predates the current wave
The two most-cited records in the corpus describe integrating silicon CMOS with AlGaN/GaN amplifiers on engineered substrates, filed years before the 2022-2024 filing peak. Newer filings are operating in claim space already shaped by this earlier CMOS-integration work.
Filing is US-weighted
The United States accounts for 25 tracked filings versus 8 for Europe, 6 for India, and 6 filed via WIPO/PCT. China and Japan each show only 2, suggesting protection in those markets is thinner relative to the underlying US-anchored R&D base.
Collaboration is limited and academic-anchored
Only 7 co-assignee pairs appear across the dataset, with the strongest links tying a university system to individual named inventors rather than to corporate co-filers. This points to a field still driven by lab-originated IP rather than joint industrial development.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gallium nitride hemt wafer bonding, with the prior art for and against each one.
Who is filing, and where they are not
Assignee activity in this dataset skews toward research institutions and a small number of corporate filers, with recent-year momentum flat across the tracked organisations.
University of California system
Appears in the co-assignee pairs with named inventors, consistent with a research-lab origin for its claims rather than a product-driven filing programme. No filings are recorded for the latest tracked year.
GlobalFoundries U.S.
One of the corporate names in the ranking, alongside Murata Manufacturing and the interuniversity microelectronics centre IMEC, none of which show filings in the most recent tracked year — consistent with the overall flat momentum across the dataset.
Indian Space Research Organisation
A government research body appearing in the assignee ranking, reflecting the India-specific receiving-office activity (6 filings) seen elsewhere in the dataset. No latest-year filings are recorded for this assignee.
| Assignee | Recent year | YoY |
|---|---|---|
| Murata Manufacturing Co., Ltd. | 0 | — |
| GlobalFoundries U.S. Inc. | 0 | — |
| Interuniversity Microelectronics Centre (IMEC) | 0 | — |
| The Regents of the University of California | 0 | — |
| Suzhou Yuannao Intelligent Technology Co., Ltd. | 0 | — |
| Indian Space Research Organisation (ISRO) | 0 | — |
| Northrop Grumman Corporation | 0 | — |
| Gaorui Technology Co., Ltd. | 0 | — |
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, competitive tracking, or identifying open claim space.
Map the citation network around the 2006-2008 core
The highest-cited records in this corpus set the CMOS-integration foundation that later filings build on. Tracing forward and backward citations from those records clarifies which claim elements are genuinely open.
Explore citation mapping in EurekaCheck freedom-to-operate on thermal-management claims
The featured record's heat-spreading and lift-off approach sits in a thinly populated branch relative to the core device classifications. A targeted claim-chart review would confirm how much room remains there.
Run a claim comparison in EurekaWatch for renewed filing activity post-2024
With 2025-2026 counts still understated by publication lag, the real trajectory since the 2024 peak will not be clear for another 12-18 months.
Set a filing alert in EurekaCommon questions about this landscape
This dataset identifies 52 patent families filed between 2015 and 2026 that combine gallium nitride HEMT device claims with wafer bonding, engineered-substrate or layer-transfer techniques. That count reflects a title/abstract/claims search using a specific query and coverage window, so a broader search on adjacent terms like buffer-layer growth or substrate lift-off alone would return a different, larger population. Families are the right unit to compare across jurisdictions since they collapse continuations and multi-country filings of the same invention into one count.
The assignee list includes a mix of universities, corporate semiconductor manufacturers and government research bodies, including the University of California system, GlobalFoundries U.S., Murata Manufacturing, the interuniversity microelectronics centre IMEC, and the Indian Space Research Organisation. None of these organisations show filings in the most recent tracked year in this dataset, which is consistent with the overall flat-to-declining filing trend rather than indicating any one of them has exited the space. Co-assignee pairings in the data are sparse and mostly link universities to named individual inventors rather than to corporate partners.
Based on this dataset, filing activity is flat rather than growing: it moved from 2 families in 2017 to a midpoint of 4 in 2022, then rose to a peak of 10 in 2024. The 2025 and 2026 figures appear low, but that is expected because patent publication typically lags the actual filing date by around 18 months, so recent years are always undercounted at the point of any search. The honest read is that this is a mature, occupied filing area rather than an emerging one, at least through the visible data.
US20230230851A1, assigned to the University of South Carolina, covers transfer of wide and ultrawide bandgap layers to an engineered substrate using 193-nm excimer laser lift-off of AlGaN/GaN HEMTs built with thick AlN heat-spreading buffer layers on sapphire. The disclosed benefit is a drop in thermal resistance from the standard sapphire-HEMT range of roughly 25-50 Kmm/W down to 16 Kmm/W as-fabricated, improving to 8 Kmm/W after soldering to a copper heat sink. Anyone designing a competing thermal-management or lift-off process for GaN-on-sapphire HEMTs should review this filing's specific claim language around the AlN layer thickness and the lift-off wavelength before assuming a clear path.
H01L, the general semiconductor devices classification, covers 50 of the 52 records in this dataset and is effectively the anchor class for this technology. H10D and H10W appear as secondary classifications at meaningfully lower counts, and H03K (pulse technique and logic circuits) plus G09G (display control circuits) show up only a handful of times each, marking where HEMT bonding work extends into circuit and display integration. A freedom-to-operate search limited to H01L alone would miss the smaller but relevant circuit-integration filings captured under H03K and G09G.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.