Gallium Oxide Vertical Power FinFET Patents 2026
Gallium Oxide Vertical Power FinFET Patents 2026
Beta-phase Ga₂O₃ FinFETs offer a theoretical breakdown field of 8 MV/cm and a Baliga figure of merit exceeding 3,000 — 10× SiC and 4× GaN. This dataset spans patent and literature records from 2016–2026 across device architectures, thermal management, and application domains.
Why Gallium Oxide Vertical FinFETs Matter for Power Electronics
Beta-phase gallium oxide (β-Ga₂O₃) offers a theoretical breakdown field of 8 MV/cm and a Baliga figure of merit exceeding 3,000 — roughly 10× that of SiC and 4× that of GaN. Melt-grown bulk substrates enable low-cost, large-area wafers unavailable to other ultra-wide-bandgap materials, creating a practical pathway to high-voltage power switching at scale.
The vertical FinFET architecture is the dominant device structure in this dataset because it achieves enhancement-mode (normally-off) operation without p-type doping. By exploiting fin geometry to electrostatically pinch off the accumulation-mode channel, it resolves the fundamental constraint that no reliable p-type doping exists for Ga₂O₃, enabling junctionless normally-off transistors.
Four interconnected innovation clusters define the field: junctionless accumulation-mode vertical FinFETs, heterojunction p-type oxide pinch-off structures using NiOₓ or Cu₂O, heterojunction CMOS platforms and cascode integration with Si or GaN, and thermal co-design approaches including substrate transfer to diamond or SiC and double-sided packaging.
Among the retrieved records, Chinese academic and research institutions account for approximately 35 of the ~50 patent records in this dataset, with Xidian University identified as the most prolific single assignee in retrieved records, holding at least 7 patents. Cornell University holds the most significant foundational US/WO jurisdiction filings, covering both fin-shaped and nanowire-shaped vertical channel architectures.
Filing Trends and Technology Cluster Distribution
Patent activity in Ga₂O₃ vertical FinFET technology has accelerated sharply since 2021, with the most recent 2024–2026 filings in this dataset pivoting toward system-level integration, thermal management, and gate-all-around architectures. The four technology clusters identified reflect distinct innovation trajectories across device architecture, materials integration, and packaging.
Technology Cluster Distribution — Ga₂O₃ Vertical FinFET (Dataset Snapshot)
Junctionless accumulation-mode vertical FinFETs represent the largest cluster in this dataset, followed by heterojunction p-type oxide gate structures and thermal/packaging innovations.
↗ Click bars to exploreFiling Activity by Period — Ga₂O₃ Vertical FinFET (Dataset Snapshot)
Filing activity in this dataset accelerated sharply in the 2021–2023 period, driven by Chinese institutional filings, with the 2024–2026 cohort pivoting toward system-level and thermal integration patents.
↗ Click bars to exploreKey Application Domains for Ga₂O₃ Vertical Power FinFETs
Retrieved patents and literature in this dataset identify four primary application areas for β-Ga₂O₃ vertical FinFET technology, spanning high-voltage industrial power conversion, electric vehicle systems, renewable energy and data center infrastructure, and UV photodetection.
High-Voltage Power Conversion (>600 V)
The primary application target across the entire dataset, with vertical FinFET structures explicitly designed for industrial motor drives, inverters, and railway traction systems. Several patents cite target voltages from 600 V to multi-kV, enabled by thick n⁻-Ga₂O₃ drift layers. Cornell University’s foundational PCT patents (2019) and Fuzhou University’s 2026 filing on high-efficiency large-power devices with comprehensive thermal dissipation both address this domain.
High-Voltage PowerElectric Vehicles and Automotive Power
Multiple patents explicitly target EV charging modules, onboard chargers, and traction inverters. Xidian University’s 2024 NiOₓ/Ga₂O₃ heterojunction FinFET patent (CN) cites applications in high-voltage transformer circuits and EV charging modules. Anhui University’s 2025 filing on a 28 nm ultra-low-power Ga₂O₃ FinFET device uses TCAD modeling directed at power converter applications including automotive systems.
Automotive ElectronicsSolar Inverters, 5G, and Data Centers
Fuzhou University’s 2023 filing integrates a Schottky barrier diode with a Ga₂O₃ FinFET for low reverse conduction loss, targeting renewable energy inverters. Quanjia Technology (Fuzhou) Co., Ltd.’s 2026 CN patent on a Ga₂O₃ power diode with junction termination extension and floating field plate composite structure cites 5G communications, AI servers, and renewable energy generation as target markets.
Renewable Energy & ICTUltraviolet Photodetection Applications
The Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences filed a 2026 CN patent on a Ga₂O₃-based fin-channel solar-blind UV phototransistor, exploiting Ga₂O₃’s wide bandgap (~4.9 eV) for solar-blind UV detection. This non-power application demonstrates adaptation of the FinFET architecture for sensing in UV-harsh environments relevant to aerospace and defense, extending the technology scope beyond power switching.
UV PhotodetectionKey Patent Assignees in Ga₂O₃ Vertical FinFET (Retrieved Records)
In retrieved records, Chinese academic and research institutions account for approximately 35 of the ~50 patent records in this dataset, with Xidian University identified as the most prolific single assignee in this dataset. Cornell University represents the most significant foundational filing presence in the US and WO jurisdictions, with government-funded coverage of both fin-shaped and nanowire-shaped vertical channel architectures.
Top Assignees by Filing Count — Ga₂O₃ Vertical FinFET in Retrieved Records (Dataset Snapshot)
↗ Click bars to exploreXidian University
The most prolific single assignee in this dataset, with at least 7 CN-jurisdiction patents filed between 2022 and 2025. Technology areas span NiOₓ/Ga₂O₃ heterojunction FinFETs, quad-surround-gate (GAA) MOSFETs on diamond substrates, thermally optimized fin-channel structures, enhancement-mode transistors with high power figure-of-merit, SOG-based diodes, and Ga₂O₃ cascode FETs based on Si MOSFET heterogeneous integration. Several patents are active as of 2025.
China — CNCornell University
Cornell University holds foundational PCT and US-jurisdiction patents on vertical Ga₂O₃ power FinFETs and nanowire FETs, filed in 2019 (WO) and granted in 2021 (US), with support from AFOSR and NSF government funding. These patents cover both fin-shaped and nanowire-shaped vertical channel architectures on β-Ga₂O₃ bulk substrates, establishing the most significant Western IP position in this dataset for vertical Ga₂O₃ power device architecture.
United States — USFive Emerging Signals from 2024–2026 Filings
Among 2024–2026 filings in this dataset, five directional signals are evident: gate-all-around geometries, complementary CMOS platform development, cascode heterogeneous integration with Si MOSFETs, diamond substrate and double-sided packaging adoption, and high-quality homoepitaxial substrate development.
Gate-All-Around (GAA) Architectures Emerging
Xidian University’s 2025 CN filing on a ‘quad-surround gate’ Ga₂O₃ MOSFET uses a diamond substrate to combine full gate-surrounding control with substrate-level thermal management, directly analogous to silicon GAA scaling. This moves beyond lateral wrap-gate toward fully surrounding gate geometries. The patent covers both the device structure and fabrication method, signaling near-term process development intent.
CMOS Platform via NiO/Ga₂O₃ Heterojunction
Southeast University’s Wuxi Integrated Circuit Technology Research Institute filed a 2025 CN patent on a fin-channel Ga₂O₃ heterogeneous CMOS platform with low power and high drive capability, integrating NiO-based PMOS with Ga₂O₃ NMOS. This extends the NiO/Ga₂O₃ heterojunction from a gate-control mechanism to a full complementary logic and gate-driver integration platform. It enables inverters and complete power-circuit functionality on a common substrate.
Ga₂O₃ Vertical FinFET vs. SiC MOSFET: Key Parameters
Click any row to explore further.
| Dimension | β-Ga₂O₃ Vertical FinFET | SiC MOSFET (Reference) |
|---|---|---|
| Bandgap | ~4.9 eV (ultra-wide) | ~3.3 eV (wide) |
| Theoretical Breakdown Field | 8 MV/cm | ~3 MV/cm |
| Baliga Figure of Merit | >3,000 (10× SiC) | ~300 (reference baseline) |
| Thermal Conductivity | ~11–27 W/m·K (low) | ~370–490 W/m·K (high) |
| Substrate Availability | Melt-grown bulk, low-cost large-area wafers possible | Mature SiC boule growth; established supply |
| P-Type Doping | Not reliably available; requires heterojunction substitutes (NiO, Cu₂O) | Available; enables conventional VDMOSFET/UMOSFET designs |
| Dominant Gate Architecture (this dataset) | Vertical FinFET with wrap-gate or GAA; junctionless accumulation-mode | Vertical DMOSFET or UMOSFET with p-well implant |
| Operating Voltage Target (patents) | 600 V to multi-kV | 600 V–1700 V (commercial mainstream) |
Frequently Asked Questions: Gallium Oxide Vertical Power FinFETs
The vertical FinFET architecture achieves enhancement-mode (normally-off) operation without p-type doping by exploiting fin geometry to electrostatically pinch off the accumulation-mode channel. This directly resolves the two fundamental constraints of Ga₂O₃: the absence of reliable p-type doping that precludes conventional junction-based vertical structures such as VDMOSFET or UMOSFET, and the need for normally-off operation without implant-based current-blocking layers.
According to the dataset, β-Ga₂O₃ has a Baliga figure of merit exceeding 3,000, which is approximately 10× that of SiC and 4× that of GaN. This is supported by a theoretical breakdown field of 8 MV/cm.
In this dataset, Xidian University (Xi’an University of Electronic Science and Technology) is the most prolific single assignee with at least 7 patents filed between 2022 and 2025, covering NiOₓ heterojunction FinFETs, gate-all-around MOSFETs on diamond substrates, thermally optimized structures, enhancement-mode transistors, and heterogeneous integration cascode configurations.
Ga₂O₃ has low thermal conductivity of approximately 11–27 W/m·K, roughly 1/10 that of silicon. Recent 2024–2026 filings in this dataset address this through substrate transfer to diamond (thermal conductivity ~2000 W/m·K) or SiC, double-sided cooling flip-chip packaging (Northwestern Polytechnical University, 2024 CN), and gate-all-around structures combined with diamond substrates (Xidian University, 2025 CN).
NiOₓ is the dominant p-type material choice in retrieved patents for forming heterojunction PN pinch-off regions at fin sidewalls or gate areas. Compared to purely electrostatic depletion, the NiOₓ/Ga₂O₃ heterojunction creates a steeper, more stable threshold voltage, enables reverse-conducting operation via built-in Schottky diode functionality, and supports CMOS-compatible complementary platforms. It is used by multiple assignees including Xidian University, Southeast University, UESTC, and Guangdong Provincial Semiconductor Industry Technology Research Institute.
Retrieved patents target four main domains: high-voltage power conversion (600 V to multi-kV) for industrial drives, inverters, and railway traction; electric vehicle charging modules, onboard chargers, and traction inverters; solar inverters, 5G communications, AI servers, and data center infrastructure; and ultraviolet (UV) solar-blind photodetection exploiting Ga₂O₃’s ~4.9 eV bandgap, as demonstrated in a 2026 CN filing from the Changchun Institute of Optics, Fine Mechanics and Physics.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.