GaN-on-Si HEMT 900V Breakdown — PatSnap Eureka
GaN-on-Si HEMT 900V Breakdown Without Thicker Buffers or Mobility Loss
Achieving 900V breakdown voltage in GaN-on-Si HEMTs for automotive power electronics requires optimizing electric field distribution, advanced field plate architectures, and innovative carrier modulation — not simply scaling buffer thickness.
Advanced Field Plate Architectures for 900V Operation
Electric field redistribution through geometric and electrostatic design — not buffer thickness — is the primary lever for reaching 900V in GaN-on-Si HEMT devices.
Integrated Slant Field Plate Architecture
The slant field plate design achieves electric field redistribution through geometric shaping rather than material modifications. Self-aligned slant field plates with rounded edges split peak electric fields into multiple smaller peaks distributed underneath the gate sidewalls. The slanted geometry — typically at acute angles of 30–45° — extends laterally from the gate, broadening the terminating points of electric fields. Fabrication involves depositing a passivation layer (typically Si₃N₄), patterning gate openings, then etching under high-pressure conditions to create slanted sidewalls before depositing gate metal with angled rotation.
Demonstrated: >1400V BV, 2.3 mΩ·cm² RₒₙMultiple Stacked Field Plate Configuration
Multi-level field plate architectures provide superior electric field shaping compared to single field plates for 900V operation. Three to four cascaded field plates are positioned at increasing distances from the gate, each connected through optimized dielectric spacing. Each field plate operates at progressively higher potentials, creating a stepped voltage distribution along the drift region. The optimal spacing follows d₁ < d₂ < d₃. Field plate lengths of 1.5–3 μm per plate and dielectric thickness of 200–500 nm (SiN or Al₂O₃) are recommended, with total drift region length of 12–18 μm for 900V rating.
Drift region: 12–18 μm for 900VCapacitance Network-Controlled Field Plates
Multiple field plates are fabricated on the same metal layer (reducing process complexity), with a capacitor network establishing predetermined potentials on each field plate. The capacitance values are calculated to achieve uniform or near-uniform field distribution: C₁:C₂:C₃ ratios typically follow 1:2:3 for three-plate systems. Static discharge impedances of 1–10 MΩ prevent charge accumulation. This approach sustains voltages exceeding 1200V with substantially uniform electric field and lower manufacturing cost via a single metal layer process.
Sustains >1200V, single metal layerHigh-K Dielectric Field Plates
Using high dielectric constant materials — Al₂O₃ (εᵣ ≈ 9) or HfO₂ (εᵣ ≈ 25) — for field plate dielectrics enhances field coupling efficiency. Higher εᵣ increases capacitive coupling between the field plate and channel, enabling shorter field plate lengths for equivalent field shaping and reducing total device area for a given breakdown voltage. Optimal dielectric thickness is 30–80 nm for field plate applications. For automotive qualification, Al₂O₃ is recommended for FP1 closest to the gate, and SiNₓ for FP2 and FP3 to balance capacitance and reliability.
Al₂O₃ for FP1, SiNₓ for FP2/FP3Lateral 2DEG Modulation Without Mobility Penalty
Creating a graded 2DEG density profile in the drift region naturally distributes electric fields more uniformly — achieving the critical goal of maintaining high mobility while improving breakdown voltage. According to patent landscape analysis, two primary techniques have emerged as most effective for automotive-grade devices.
Ion Implantation-Based Modulation: Gray-scale photolithography creates a tapered mask with thickness increasing from gate toward drain. Light ion implantation — typically Nitrogen or Argon at doses of 10¹²–10¹³ cm⁻² — through the graded mask induces controlled lattice damage in the AlGaN barrier layer. The damage is confined to the top 5–10 nm of the AlGaN barrier, leaving the GaN channel layer pristine. This achieves flat electric field distribution with peak field reduction of 30–40% and breakdown voltage improvement of 2–3× compared to uniform 2DEG structures. The figure of merit (BV²/Rₒₙ) enhancement exceeds 5×.
Stress-Induced Piezoelectric Modulation: A stress-inducing layer — typically SiNₓ with controlled intrinsic stress — is deposited on the AlGaN barrier. Patterning this layer with varying opening sizes or thickness profiles modulates local stress. The stress variation changes the piezoelectric polarization in the AlGaN barrier, thereby controlling 2DEG density. This approach introduces zero scattering centers, maintaining full 2DEG mobility of 2000+ cm²/V·s. Stress layer thickness variation of 50–200 nm over 10–15 μm drift length achieves 2DEG density variation from 8×10¹² to 1.2×10¹³ cm⁻² across the drift region. The technique is compatible with high-temperature automotive qualification up to 175°C junction temperature.
Ion implantation dose must remain below 5×10¹³ cm⁻² to avoid excessive scattering, and stress layer-induced strain must be limited to <0.3% to prevent defect generation. The IEEE has published extensively on the relationship between piezoelectric polarization and 2DEG density in III-nitride heterostructures.
Key Performance Metrics Across Design Strategies
All values derived from patent and literature analysis via PatSnap Eureka. Charts show the quantitative impact of each engineering approach.
2DEG Mobility Retention by Modulation Technique
Stress-induced piezoelectric modulation preserves full 2DEG mobility (>2000 cm²/V·s), while ion implantation at optimized doses maintains above 1800 cm²/V·s.
Buffer Composition Optimization (No Thickness Increase)
Replacing uniform GaN buffer with superlattice structures and optimized C-doping profiles enhances vertical breakdown field up to 3 MV/cm vs. 2 MV/cm for bulk GaN.
Edge Termination, Passivation, and Gate Innovations
Optimizing the passivation layer and gate structure provides additional electric field management mechanisms without altering the buffer or 2DEG channel.
| Technique | Mechanism | Key Parameter | Performance Gain | Automotive Fit |
|---|---|---|---|---|
| Charged Passivation Layer | Negative fixed charges (1–3×10¹² cm⁻²) in SiNₓ create compensating field along drift region | N/Si ratio controls charge density | Reduces peak gate-edge field by 25–35%; improves BV by 200–400V | ✓ Compatible |
| Large Gate Metal Height | Gate metal height 0.5–1.5 μm (vs. conventional 0.2–0.3 μm) creates integrated field plate effect | Gate height 0.5–1.5 μm | BV enhancement 15–25% for same drift length; combinable with separate FPs | ✓ Compatible |
| p-GaN Gate (E-mode) | Thin p-GaN layer (50–100 nm) beneath gate depletes 2DEG; acts as field management element | Threshold voltage +1 to +3V | BV improvement 10–20% vs. Schottky gate E-mode; lower gate leakage | ✓ Normally-off |
| Al₂O₃ Field Plate Dielectric | εᵣ ≈ 9 increases capacitive coupling; enables shorter FP lengths for equivalent shaping | Thickness 30–80 nm | Reduced device area; excellent interface quality and reliability | Recommended FP1 |
Map the Complete GaN Passivation Patent Landscape
PatSnap Eureka surfaces the patents behind every passivation and gate technique in seconds.
Recommended Multi-Technique Architecture for 900V Automotive
Reliable 900V operation requires combining field plate engineering, 2DEG grading, passivation optimization, and buffer composition — not any single technique alone.
Three-Level Field Plate Configuration
FP1 (gate-connected, 2 μm) · FP2 (source-connected or capacitively coupled, 3 μm length, 4 μm from gate edge) · FP3 (source-connected or capacitively coupled, 4 μm length, 9 μm from gate edge). Gate-to-drain spacing: 15–20 μm. Gate length: 1.5–2 μm. This configuration distributes the electric field across the full drift region without requiring a single oversized plate that would excessively increase Cgd.
2DEG Density Grading in Drift Region
Implement stress-induced or ion-implantation-based 2DEG grading. Target 2DEG density variation: 8×10¹² cm⁻² near gate to 1.2×10¹³ cm⁻² near drain. This maintains sheet resistance while distributing the electric field. Combine moderate 2DEG grading (30–40% variation) with optimized field plates and validate dynamic Rₒₙ remains within 20% of DC Rₒₙ under pulsed operation.
Process Integration and Automotive Qualification
Achieving 900V breakdown in production requires not only the right device architecture but rigorous process control. Yield and reliability engineering are as critical as the device design itself for automotive-grade GaN power devices.
Critical Process Steps: Buffer growth uses MOCVD with in-situ SiH₄ doping for carbon incorporation. 2DEG modulation — stress layer patterning or ion implantation — is implemented after ohmic contact formation. Field plate formation requires multi-layer metallization with careful CMP and via processing. Passivation uses plasma-enhanced CVD with controlled deposition conditions for charge engineering.
Yield-Critical Parameters: Field plate alignment tolerance must be held to ±0.3 μm for reliable 900V operation. Passivation pinhole density must remain below 0.1 cm⁻² to prevent premature breakdown. Ohmic contact resistance must be kept below 0.3 Ω·mm to minimize parasitic losses.
Automotive Qualification Requirements: High-temperature reverse bias (HTRB) at 80% of rated voltage at 150°C for 1000 hours. Temperature cycling from -40°C to +175°C for 1000 cycles. Humidity testing at 85°C/85% RH for 1000 hours. These requirements are consistent with JEDEC automotive reliability standards for power semiconductors. The IEC also provides relevant qualification frameworks for wide-bandgap power devices.
For switching applications targeting 50–200 kHz frequencies, Cgd should remain below 200 pF/mm. Using three shorter field plates rather than one long plate is the optimal strategy for this constraint, as documented in PatSnap's patent analytics for the GaN power device space.
GaN-on-Si HEMT 900V Breakdown — key questions answered
The slant field plate design has demonstrated breakdown voltages exceeding 1400V with on-resistance as low as 2.3 mΩ·cm² in enhancement-mode devices. The field redistribution mechanism maintains 2DEG integrity since the modulation occurs through electrostatic effects rather than channel disruption.
The 2DEG forms at the AlGaN/GaN interface, and the electron transport occurs primarily in the undoped GaN channel. Surface lattice damage modulates the piezoelectric polarization without introducing scattering centers in the electron transport path. Mobility typically remains above 1800 cm²/V·s, compared to 1900–2000 cm²/V·s in unmodified structures.
For 900V rating, a gate-to-drain spacing of 15–20 μm is recommended in the lateral structure, combined with a three-level field plate configuration and optimized drift region length of 12–18 μm.
Optimized carbon doping profiles in the existing buffer can significantly reduce buffer leakage without thickness changes. A carbon concentration of 1–5×10¹⁷ cm⁻³ in the bulk buffer with a lower concentration of 5×10¹⁶ cm⁻³ in the top 200 nm reduces buffer leakage current by 2–3 orders of magnitude and increases vertical breakdown voltage by 30–50%.
Automotive qualification requires high-temperature reverse bias (HTRB) at 80% of rated voltage at 150°C for 1000 hours, temperature cycling from -40°C to +175°C for 1000 cycles, and humidity testing at 85°C/85% RH for 1000 hours. Design margins target 1000V breakdown for 900V applications (11% margin) and threshold voltage shift below 0.3V over lifetime.
The integrated multi-technique approach enables reliable 900V operation with on-resistance in the 2.5–3.5 mΩ·cm² range and mobility preservation above 1800 cm²/V·s, meeting the stringent requirements of automotive power electronics applications.
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References
- A high electron mobility field effect transistor and method of manufacturing the same — PatSnap Eureka Patent
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- Breakdown voltage enhancement in GaN channel and AlGaN channel HEMTs using large gate metal height — PatSnap Eureka Literature
- Recent advances in GaN-based power devices and integration — IOP Science / Semiconductor Science and Technology
- JEDEC — Automotive Reliability Standards for Power Semiconductors
- IEC — International Electrotechnical Commission, Wide-Bandgap Power Device Qualification Frameworks
- IEEE — Piezoelectric Polarization and 2DEG Density in III-Nitride Heterostructures
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