GaN Power Module Packaging Landscape 2026 — PatSnap Eureka
GaN Power Module Packaging Technology Landscape 2026
Gallium nitride power module packaging is converging on co-packaged driver architectures, ceramic substrates, and direct liquid cooling — driven by the need to minimize parasitic inductance at 500 kHz–1 MHz switching frequencies. Explore the full patent and literature landscape with PatSnap Eureka.
Why GaN Power Module Packaging Matters
Gallium nitride power module packaging encompasses the structural, thermal, electrical, and mechanical engineering required to house GaN transistors — primarily high-electron-mobility transistors (HEMTs) operating in lateral configurations — within modules capable of handling high switching speeds, elevated junction temperatures, and high power densities.
The literature confirms that GaN devices can operate at frequencies up to 1 MHz with substantially lower switching losses than silicon IGBTs, but that discrete PCB-mounted configurations introduce excessive parasitic inductance through long routing traces — a problem that module-level integration specifically addresses. A review from Politecnico di Torino notes that "high-electron-mobility transistors based on gallium nitride technology are the most recently developed power electronics devices involved in power electronics applications," while underscoring that parasitic effects during fast switching transitions represent the dominant performance limiter at the package level.
The four core technical challenges consistently identified across this dataset are: minimizing parasitic inductance and capacitance in the switching loop; managing heat generated at GaN device hot spots; ensuring reliable die bonding and interconnect under thermal cycling; and achieving compact integration with gate driver circuits. Teams working in advanced materials and power electronics will find these challenges are deeply interconnected — substrate selection, interconnect strategy, and thermal architecture must be co-optimized.
The PatSnap patent analytics platform identifies at least 15 distinct active assignees across this dataset, spanning Chinese GaN integration specialists, Japanese substrate innovators, European energy companies, and US WBG module designers — confirming that no single player dominates this rapidly evolving space.
Patent Landscape at a Glance
Key quantitative signals from the GaN power module packaging patent and literature dataset spanning 2000–2026, analyzed via PatSnap Eureka.
GaN Module Patent Filing Activity by Innovation Era
The dataset shows a distinct concentration of GaN-specific module patents filed between 2020 and 2026, confirming rapid maturation of the technology cluster.
Patent Jurisdiction Distribution in Dataset
Chinese assignees hold the highest concentration of GaN-specific integration patents; Japanese and European assignees lead in substrate and thermal innovations.
GaN Module Application Domain Focus
Consumer electronics and automotive represent the primary application targets in the dataset, with industrial and computing applications growing rapidly.
GaN Module Packaging Integration Roadmap
The packaging boundary is shifting inward — from discrete PCB placement toward co-packaged driver + GaN + protection at die level, compressing the system further.
Four Patent Clusters Defining GaN Module Packaging
The dataset reveals four distinct innovation clusters, each addressing a different facet of the parasitic minimization, thermal management, and integration challenge.
PCB-Embedded GaN Module with Co-Packaged Driver
GaN power transistors are placed on the reverse face of a PCB directly opposite their gate driver chips, with a direct bonded copper (DBC) ceramic substrate mounted on the GaN device face for heat extraction. The encapsulant covers the PCB, driver, and GaN device stack while exposing the ceramic substrate's outer face for external cooling. Suzhou Liang Wei Semiconductor (2025, 2020) and Suzhou Liangyao Semiconductor (2020) hold the key filings. This architecture claims substantially reduced parasitic inductance compared to discrete PCB placement, with GaN transistors capable of 500 kHz–1 MHz operation.
↓ Parasitic inductance vs discrete PCBIntegrated GaN Module with Thermal Transfer Substrate
Apple Inc. developed an integrated GaN module in which one or more GaN transistors are sandwiched between a PCB (second surface) and a thermal transfer substrate, with spacers soldered to both to maintain mechanical alignment. Surface-mount components occupy the PCB first surface. This approach prioritizes compact form factor for consumer electronics and eliminates traditional wire bonding entirely — targeting the mid-power smartphone and laptop adapter market where GaN adapters have already achieved mass production.
Wire-bond-free · Consumer electronicsGaN Intelligent Power Module with Stacked Die
The GaN transistor is stacked directly on top of its gate driver die, with source and gate pads of the GaN device directly contacting the output and ground pads of the driver — eliminating wire bonds entirely. The structure is enclosed in a thermally conductive opaque encapsulant. Midea Group pioneered this approach in China (2017). Apex Technology's JP filing (2022) further claims reduced parasitic impedance in the driver circuit through an insulated heat dissipation substrate with multiple power devices and a control chip with gate drive and PWM functions.
Face-to-face stacking · Zero wire bondsAdvanced Substrate and Thermal Management Architectures
This cluster addresses the substrate and thermal path beneath GaN devices — using silicon nitride, aluminum nitride, or alumina ceramics with copper or silver circuit layers. Mitsubishi Electric R&D Centre Europe's 2024 JP filing introduces via density grading as a thermal equalization tool — reducing via density from hot spots to the periphery to balance mechanical stress and temperature. Murata's EP filing (2023) combines a glass-ceramic multilayer control substrate directly on a highly thermally conductive ceramic substrate. Delta Electronics (Shanghai)'s EP filing (2024) introduces a second substrate elevation to reduce jumping electrode parasitic capacitance, directly targeting EMI.
Via density grading · SiN vs AlN bifurcationFive Convergent Trends from 2023–2026 Filings
The most recent patent filings in this dataset reveal structural shifts in how GaN power modules are designed, assembled, and integrated.
Substrateless Lead-Frame-First Assembly
India VP Semiconductor Private Limited's JP filing (2025) eliminates the conventional ceramic substrate by using PCB as the primary structural element with bus bars, insulating layers, and heat dissipation layers stacked below it. This radically simplifies assembly flow and reduces component count — a significant cost-reduction signal for volume manufacturing.
Hot-Spot-Adaptive Via Density in Substrates
Mitsubishi Electric R&D Centre Europe's 2024 JP filing introduces via density grading as a thermal equalization tool — reducing via density from hot spots toward the periphery to balance mechanical stress and temperature distribution, extending module lifetime. This represents a design-rule innovation directly applicable to GaN dies operating at high power density.
Where GaN Packaging Innovation is Concentrated
Within this dataset, innovation is distributed across four geographic clusters with distinct specializations. The highest concentration of GaN-specific module packaging patents originates from Chinese assignees. PatSnap Eureka's patent analytics shows Suzhou Liang Wei Semiconductor Co., Ltd. and Suzhou Liangyao Semiconductor Co., Ltd. account for at least 3 closely related GaN PCB-sandwich module patents (2020, 2020, 2025), indicating iterative development of the same core architecture. Guangdong Midea Refrigeration Equipment Co., Ltd. (2017, CN) filed an early GaN IPM stacking patent, and Apple Inc.'s CN filing (2024) adds a multinational dimension.
In Japan, Mitsubishi Electric Corporation filed two active JP-jurisdiction records consistent with its historically dominant position in power module packaging. Murata Manufacturing Co., Ltd. (EP, 2023) and Mitsubishi Electric R&D Centre Europe B.V.'s thermally improved PCB patent (JP, 2024) demonstrate Japan as a registration jurisdiction for European R&D outcomes. The European Patent Office jurisdiction hosts Delta Electronics, Hitachi Energy Switzerland AG (EP, 2026), and Murata Manufacturing filings — with Hitachi Energy's 2026 EP filing representing the most recent in the dataset.
In the United States, wide-bandgap semiconductor leaders including Wolfspeed, Inc. (formerly Cree, Inc.) hold multiple active US design patents for power semiconductor packages (2022, 2023, 2024), and Rohm Co., Ltd. maintains a dense portfolio of US design patents across 2019–2023. Infineon Technologies AG holds active US design registrations (2019).
A key observation: innovation is not concentrated in a single player. In this dataset, at least 15 distinct active assignees hold relevant packaging records — a strong signal that the GaN power module packaging space remains competitive and open to new entrants. PatSnap customers in this space use Eureka to monitor competitor filing patterns and identify white-space opportunities across all four jurisdictions simultaneously.
What the GaN Packaging Patent Landscape Means for R&D Teams
Five actionable signals derived from the patent and literature dataset for IP strategists, product developers, and R&D leaders.
GaN Power Module Packaging — Key Questions Answered
GaN power module packaging encompasses the structural, thermal, electrical, and mechanical engineering required to house GaN transistors — primarily high-electron-mobility transistors (HEMTs) operating in lateral configurations — within modules capable of handling high switching speeds, elevated junction temperatures, and high power densities.
GaN devices can operate at frequencies up to 1 MHz with substantially lower switching losses than silicon IGBTs. The PCB-embedded GaN module architecture claims GaN transistors capable of 500 kHz–1 MHz operation and high power density.
The core technical challenges consistently identified are: (1) minimizing parasitic inductance and capacitance in the switching loop, (2) managing heat generated at GaN device hot spots, (3) ensuring reliable die bonding and interconnect under thermal cycling, and (4) achieving compact integration with gate driver circuits.
In this dataset, at least 15 distinct active assignees hold relevant packaging records. Chinese assignees dominate GaN-specific integration patents — Suzhou Liang Wei Semiconductor Co., Ltd. and Suzhou Liangyao Semiconductor Co., Ltd. account for at least 3 closely related GaN PCB-sandwich module patents. Japanese and European assignees including Mitsubishi Electric, Murata, and Hitachi Energy lead in substrate and thermal innovations. US assignees including Wolfspeed and Rohm concentrate in design patents and WBG performance module architectures.
Murata's EP filing explicitly claims silicon nitride, aluminum nitride, alumina, and silicon carbide as substrate options. Ceramic substrate material selection is bifurcating between silicon nitride (high mechanical strength) and aluminum nitride (high thermal conductivity). For GaN modules targeting automotive temperature ranges, silicon nitride's combination of thermal conductivity and fracture toughness is advantageous.
The most recent filings (2023–2026) reveal: substrateless and lead-frame-first module assembly; hot-spot-adaptive via density in substrates; fluid-cooled sandwich semiconductor power modules; smart GaN ICs with integrated protection and sensing (such as Cambridge GaN Devices' ICeGaN); and EMI-optimized multi-substrate stacking to reduce parasitic capacitance from switching nodes.
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References
- High-Performance Packaging Technology for Wide Bandgap Semiconductor Modules — Anonymous, 2018
- Packaging Structure for Power Module — Delta Electronics (Shanghai) Co., Ltd., 2024, EP
- Automotive Power Module Packaging: Current Status and Future Trends — McMaster University, 2020
- High Performance Silicon Carbide Power Packaging — Past Trends, Present Practices, and Future Directions — University of Arkansas, 2017
- A Technology Overview of the PowerChip Development Program — Massachusetts Institute of Technology, 2013
- IEEE ITRW Working Group Position Paper — Packaging and Integration: Unlocking the Full Potential of Wide-Bandgap Devices — University of Cambridge, 2018
- Power Module Semiconductor Package and Semiconductor Device — Mitsubishi Electric Corporation, 2025, JP
- Power Module (GaN PCB Sandwich) — Suzhou Liang Wei Semiconductor Co., Ltd., 2025, CN
- Power Module (GaN PCB Sandwich) — Suzhou Liangyao Semiconductor Co., Ltd., 2020, CN
- Power Module (GaN PCB Sandwich) — Suzhou Liang Wei Semiconductor Co., Ltd., 2020, CN
- Integrated GaN Power Module — Apple Inc., 2024, CN
- Power Assembly, Manufacturing Method, and GaN Intelligent Power Module — Guangdong Midea Refrigeration Equipment Co., Ltd., 2017, CN
- Intelligent Power Module Packaging Structure — Apex Technology Co., Ltd., 2022, JP
- Thermally Improved PCB for Power Semiconductor Dies Connected by Via Technology — Mitsubishi Electric R&D Centre Europe B.V., 2024, JP
- Power Module and Manufacturing Method Thereof — Murata Manufacturing Co., Ltd., 2023, EP
- GaN Power Devices: Current Status and Future Challenges — Panasonic Corporation, 2019
- ICeGaN Technology: The Easy-to-Use and Self-Protected GaN Power IC — Cambridge GaN Devices Ltd., 2023
- Building Blocks for GaN Power Integration — Fraunhofer Institute for Applied Solid State Physics (IAF), 2021
- Gallium Nitride Power Devices in Power Electronics Applications: State of Art and Perspectives — Politecnico di Torino, 2023
- Semiconductor Power Module, Semiconductor Power Package and Method for Manufacturing — Hitachi Energy Ltd., 2025, EP
- Power Module and Method for Producing a Power Module — Hitachi Energy Switzerland AG, 2026, EP
- Substrate-less Hybrid Power Module Assembly and Method of Manufacturing Same — India VP Semiconductor Private Limited, 2025, JP
- Double-Sided Cooling Power Module and Its Manufacturing Method — LG Electronics Inc., 2023, JP
- Power Module and Manufacturing Method Thereof — Delta Electronics, Inc., 2021, EP
- Power Semiconductor Packaging Method and Structure — General Electric Company, 2019, EP
- The Characterization and Application of Chip Topside Bonding Materials for Power Modules Packaging: A Review — NARI-GEIRI Semiconductor Co., Ltd., 2020
- Semiconductor Power Module for Vehicles — Semikron Danfoss International GmbH, 2025, US
- IEEE — Power Electronics Society: Wide-Bandgap Semiconductor Resources
- European Patent Office — Power Semiconductor Patent Classifications
- Politecnico di Torino — GaN Power Devices Research Group
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform. This landscape is derived from patent and literature records retrieved across targeted searches and represents a snapshot of innovation signals within this dataset only.
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