Gate All Around Nanosheet Patents: Who Leads, Where the Gaps Are 2026
- 68.0% concentration at the top. The top 5 of the ranked assignees account for 1,789 of the 2,629 records in scope — a claim map dominated early by a small set of filers.
- Filings hold steady, not falling. 2021's 385 records moved to 346 in 2024, a -10% span over that period; 2025-2026 figures are still filling in given the usual ~18-month publication lag.
- One record carries outsized influence. US20140225065A1 is cited 817 times, more than double the next most-cited record, and still sits upstream of most inner-spacer and sheet-release claims filed since.
Filing growth compares 2021 (385 records) with 2024 (346) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 2,629 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
This landscape tracks patent families addressing gate-all-around and nanosheet transistor architecture — structures built around stacked channel sheets rather than a single fin or planar channel — narrowed to records that also claim inner spacer formation, sheet release, width scaling, work function patterning, parasitic capacitance control, or variability control. These are the process steps that separate a working nanosheet device from a theoretical one: releasing the sacrificial layers between sheets, protecting the gate from the source/drain regions, and tuning threshold voltage sheet by sheet.
The scope spans 2,629 published records filed between 2015 and mid-2026, drawn primarily from US filings with meaningful PCT, European, Indian and Taiwanese activity. Because families rather than raw document counts are ranked, the concentration figures below reflect distinct invention families, not continuation volume.
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Filing trends and technology composition
Two views of the same 2,629-record dataset: how filing activity moved year over year, and which IPC subclasses carry the claims.
Filing trend, 2017-2026
Filings rose from 90 in 2017 to a peak of 421 in 2022, then eased to 346 by 2024 — a -10% move across the 2021-2024 span. 2025 and 2026 figures (down to 34 so far) are undercounts still catching up to the publication lag, not evidence of a slowdown.
Technology composition by IPC subclass
H01L (semiconductor devices) touches 75.8% of the 2,629 records and H10D (semiconductor devices, general) touches 45.9% — expected given both are broad device classes that nanosheet claims inherently sit inside. The more diagnostic classes are the smaller ones: H10B memory manufacture at 11.3%, B82Y nanotechnology at 4.5%, and G06F digital processing at 3.8%, each pointing to a specific downstream application rather than the base transistor structure.
Shares are the percentage of the 2,629 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Gate All Around Nanosheet Transistors with Eureka
This page is one run against one query. Ask Eureka your own question about gate all around nanosheet transistors and every answer comes back with the patent numbers behind it.
Try EurekaThe records anchoring this field
Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness
Nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpness generally include a bilayer spacer adjacent a dummy gate disposed on a nanosheet stack. The bilayer spacer includes an inner spacer layer on sidewalls of the gate and a sacrificial layer on the inner spacer layer. The sacrificial layer can be laterally trimmed to bring the in situ doped source/drain regions closer to the channel, which improves junction sharpness. Additionally, the sacrificial spacer layer can be later removed during the process for forming the transistor so as to form an airgap spacer adjacent the gate, which minimizes parasitic capacitance.Filed by International Business Machines Corporation, published 2020-06-09.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20140225065A1 | Non-planar gate all-around device and method of fabrication thereof | 817 |
| 2 | US20120138886A1 | Silicon and silicon germanium nanowire structures | 399 |
| 3 | US20190393304A1 | DIELECTRIC ISOLATION AND SiGe CHANNEL FORMATION FOR INTEGRATION IN CMOS NANOSHEET CHANNEL DEVICES | 327 |
| 4 | US20060240622A1 | Multi-channel semiconductor device and method of manufacturing the same | 231 |
| 5 | US20060076625A1 | Field effect transistors having a strained silicon channel and methods of fabricating same | 213 |
| 6 | US20170040321A1 | Gate-all-around nanowire device and method for manufacturing such a device | 206 |
| 7 | US9640531B1 | Semiconductor device, structure and methods | 163 |
| 8 | US20190244933A1 | 3D semiconductor device and structure | 158 |
| 9 | US10263100B1 | Buffer regions for blocking unwanted diffusion in nanosheet transistors | 154 |
| 10 | US20170194430A1 | Method for fabricating nanowires for horizontal gate all around devices for semiconductor applications | 153 |
Ranked by citation count within this search corpus; older filings accumulate citations simply by being available longer, so treat this as a signal of influence on later claim drafting, not of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for filing strategy
Three patterns worth acting on before drafting the next claim in this space.
Claim space is front-loaded
The top 5 of the ranked assignees hold 1,789 of the 2,629 records in scope, and the top 10 extend that to 84.8%. New entrants are filing into a field where the largest, most defensible structural claims on inner spacer formation and sheet release are already staked out.
Activity has plateaued, not collapsed
Filings ran from 385 in 2021 to 346 in 2024, a modest pullback from the 2022 peak of 421. That reads as a maturing structural base rather than retreat — most leading assignees show sharp year-over-year drops in the latest partial year, consistent with the publication lag rather than an actual pullback.
One foundational structure dominates prior art
US20140225065A1's citation count is more than double the second most-cited record in scope. Freedom-to-operate work in this field should treat it as the default starting point for any non-planar gate-all-around fabrication claim.
Filing activity is US-centric with a PCT tail
The United States receiving office accounts for the large majority of filings, with WIPO (PCT), European, Indian and Taiwanese offices trailing well behind. Regional strategy should weight US prosecution first, then decide selectively on PCT extension.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gate all around nanosheet transistors, with the prior art for and against each one.
Who is filing, and where the field is still open
A small set of assignees hold most of the structural claim space, but momentum has slowed across nearly all of them in the latest reported year, and several process sub-areas remain thin.
One filer sets the pace
The top-ranked assignee holds 998 of the 2,629 records in scope, well ahead of fifth place at 125 and tenth place at 53 — a steep drop-off after the leader rather than a gradual taper.
Even leaders are pulling back in the latest year
The top assignee filed 20 records in the latest year, down 83% year over year; smaller filers show similarly steep drops. This tracks the publication lag more than a real change in R&D investment, but it means the latest-year counts should not be read at face value.
Co-filing is limited and mostly internal
The strongest co-assignee pairs link a company with its own overseas IP or subsidiary units, plus one university-industry pairing. Cross-company joint filing is rare in this field, which suggests most structural know-how is being kept in-house rather than pooled.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 20 | -83% |
| Semiconductor Energy Laboratory Co., Ltd. | 3 | -70% |
| Applied Materials, Inc. | 2 | -89% |
| International Business Machines Corporation (IBM) | 1 | -90% |
| Samsung Electronics Co., Ltd. | 1 | -95% |
| Yangtze Memory Technologies Co., Ltd. | 1 | -88% |
| Intel Corporation | 0 | -100% |
| SILVEBROOK KIA | 0 | -100% |
Where to take this analysis
The dataset points to a field with a settled top tier and specific process gaps still open beneath it.
Map freedom-to-operate against the leading families
Before drafting new inner-spacer or sheet-release claims, run a citation-aware search against the most-cited records in this set, starting with the two structural patents that anchor most later filings.
Explore in EurekaTrack the under-claimed sub-areas
Sheet-count-specific work function tuning and variability control across stacked sheets show thinner coverage than the core structural claims — a narrower opportunity window before the leading filers close it.
Explore in EurekaWatch the next 18 months of publications
Filing counts for 2025-2026 are still incomplete due to publication lag; re-run this landscape once those years settle to see whether the 2021-2024 plateau holds or resumes climbing.
Explore in EurekaCommon questions about this landscape
One assignee leads the ranked list with 998 of the 2,629 records in scope, far ahead of the fifth-ranked filer at 125 and the tenth at 53. The top 5 assignees combined hold 68.0% of all records, and the top 10 combined hold 84.8%, meaning the field is concentrated among a handful of large semiconductor manufacturers and foundries rather than spread evenly. Smaller filers make up a long tail beyond that top 10, each contributing a modest number of families.
Filings grew from 90 in 2017 to a peak of 421 in 2022, then eased to 346 by 2024 — a -10% change across that later three-year span, not a collapse. Figures for 2025 and 2026 look lower still, but that reflects the roughly 18-month lag between filing and publication rather than an actual drop in R&D activity. The fairest read is a plateau following a rapid build-out phase, with the true 2025-2026 picture not yet visible in published data.
US10679906B2, assigned to International Business Machines Corporation and published 2020-06-09, claims a nanosheet transistor structure using a bilayer spacer next to a dummy gate: an inner spacer layer plus a sacrificial layer that can be trimmed to bring source/drain regions closer to the channel and later removed to leave an airgap spacer. The stated benefits are improved junction sharpness and reduced parasitic capacitance. Anyone designing an inner-spacer or airgap-spacer process for nanosheet devices should review this claim set specifically, since it targets exactly that fabrication step.
Relative to the dense core structural claims around basic gate-all-around fabrication, sub-areas such as sheet-count-specific work function tuning, inner spacer material selectivity for sub-5nm gaps, variability control across stacked sheet counts, and width-scaling for wide-sheet power devices show comparatively thin coverage. These are process-level refinements rather than the base architecture, and they intersect with the smaller IPC classes in this dataset such as B82Y nanotechnology and G06F digital processing rather than the dominant H01L and H10D classes. That combination of technical specificity and lower filing density is where a new claim is more likely to find open space.
H01L, the general semiconductor devices class, touches 75.8% of the 2,629 records in scope, and H10D, semiconductor devices in general, touches 45.9% — both expected since nanosheet structures are inherently semiconductor devices. More diagnostic are the smaller classes: H10B memory device manufacture at 11.3%, H10W at 10.2%, G11C static and digital memories at 4.6%, and B82Y nanotechnology applications at 4.5%, each signalling a specific downstream application layered on top of the base transistor claims.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.