Gate-All-Around Transistor Gate Dielectric Patents: Top Companies 2026
Patent landscape analysis of gate-all-around transistor gate dielectric technology: filing trends, leading assignees, IPC composition and white space, based on 92 records to 2026.
Filing growth = 2021 (11 records) → 2024 (10); 2024 is the last year we treat as complete. Top-5 share = the 5 largest assignees ÷ all 92 records in scope (CR5), not the ranked leaders only.
What the gate dielectric filing record shows
Gate-all-around (GAA) transistor architecture replaces the planar or FinFET channel with a fully wrapped gate, and the dielectric layer that separates that gate from the channel carries much of the electrical performance risk — leakage, threshold voltage control, and reliability under scaling all trace back to how that layer is built. The 92 records in scope, spanning 2015 through the 2026 cut-off, sit almost entirely inside H01L (84.8% of records) with nearly half also tagged H10D, the newer semiconductor-devices subclass that has absorbed part of the H01L docket as classification schemes evolve.
Filing activity rose through the late 2010s, peaked in 2019, and has since settled into a lower but still active band. Publication lag means the most recent one to two years understate real filing activity, so the 2021-to-2024 comparison — a -9% change — is the most reliable recent read rather than any single latest-year count.
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Filing trend, assignee concentration and technology mix
Three views of the same 92-record dataset: how filings moved year over year, who holds the largest share of that activity, and which IPC subclasses the records fall under.
A 2019 peak followed by a plateau
Filings climbed from 7 in 2017 to a peak of 14 in 2019, then eased. The 2021-to-2024 window — the last stretch with mostly complete publication — moved from 11 to 10 records, a -9% change; treat 2025 and 2026 figures as still filling in rather than a genuine drop-off.
Publication lags filing by roughly 18 months, so 2025 onwards are still filling in. Growth rates on this page therefore end at 2024; running them to the last bar would understate the field.
H01L dominance with a growing H10D overlap
H01L covers 84.8% of the 92 records and H10D 47.8%, reflecting how the classification of GAA structures has split across the legacy and reorganised semiconductor-device subclasses. B82Y (nanotechnology applications) appears on 18.5% of records, and H10P, H10B, G03F and G11C each cover a single-digit-to-low-double-digit share — these are the branches where claim density is lighter.
Shares are the percentage of the 92 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Gate-All-Around Transistor Gate Dielectric Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about gate-all-around transistor gate dielectric patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records and a representative filing
Gate All Around Transistors for Different Applications (US20210083054A1)
Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a plurality of first channel members and a first gate dielectric layer over the plurality of first channel members, and a second GAA transistor that includes a plurality of second channel members, and a second gate dielectric layer over the plurality of second channel members. A first width (W1) of each of the plurality of first channel members is greater than a second width (W2) of each of the plurality of second channel members. A first thickness (GL1) of the first gate dielectric layer is smaller thaAbstract truncated as provided in the source record.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20200105929A1 | Gate-all-around field-effect transistor with asymmetric threshold voltage | 85 |
| 2 | US20200105752A1 | Semiconductor structure having gate-all-around devices | 47 |
| 3 | US20200258785A1 | Quadruple gate dielectric for gate-all-around transistors | 32 |
| 4 | US20210083054A1 | Gate All Around Transistors for Different Applications | 24 |
| 5 | US20160013309A1 | Semiconductor device having gate-all-around transistor and method of manufacturing the same | 24 |
| 6 | US20160190233A1 | Transistor with wurtzite channel | 16 |
| 7 | CN111435641A | 三维堆叠的环栅晶体管及其制备方法 | 11 |
| 8 | US20170236901A1 | Junctionless Transistor Based on Vertically Integrated Gate-All-Round Multiple Nanowire Channels and Method o… | 11 |
| 9 | CN114242780A | 氧化铟锡垂直型环栅场效应晶体管及其制备方法 | 10 |
| 10 | US20180151669A1 | Iii-v semiconductor layers, iii-v semiconductor devices and methods of manufacturing thereof | 10 |
Citation counts favour older records simply because they have had more time to accumulate citations inside the searched corpus — read them as a signal of influence on later filings, not as a ranking of current commercial relevance.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Four read-throughs from the assignee ranking, the trend, and the IPC composition — useful for deciding where a new filing is likely to face dense prior art versus where it is not.
The field is led, not fragmented
Five assignees account for 66.3% of the 92 records in scope, and the top ten extend that to 84.8%. A ranking this concentrated means most core dielectric-layer claim space around GAA structures is already staked by a small group of large semiconductor manufacturers and a handful of research institutes.
Activity has plateaued, not collapsed
After peaking at 14 records in 2019, filings settled into a lower band; the 2021-to-2024 comparison shows a -9% change, the last period with reliable publication coverage. Treat any apparent drop in 2025-2026 as a lag artefact, not a real slowdown.
Nanotechnology-adjacent claims are a minority track
Only 18.5% of the 92 records carry the B82Y nanotechnology-applications tag, versus 84.8% for H01L. Filings that frame GAA gate dielectric work through a nanotechnology-application lens rather than a conventional semiconductor-device lens sit on comparatively lighter prior art.
Cross-institution filing is rare but concentrated
Only four co-assignee pairings appear across the dataset, and the strongest links university research groups to manufacturing-innovation centres rather than to competing manufacturers — a pattern more consistent with joint R&D programmes than with cross-licensing.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gate-all-around transistor gate dielectric patent landscape, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Fudan University | Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd. | 3 |
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | National Taiwan University | 2 |
| Beijing Superstring Academy of Memory Technology | Peking University | 2 |
| Institute of Microelectronics, Chinese Academy of Sciences | Beijing Superstring Academy of Memory Technology | 1 |
The strongest co-assignee pairs link a university department to an affiliated manufacturing-innovation centre, suggesting joint research programmes rather than arm's-length licensing between competitors.
Where to take this analysis
The dataset points to a concentrated core and a thinner set of adjacent branches. These are the next steps worth taking with either.
Map the white space claim by claim
Under-represented subclasses like H10P, H10B and G03F are lighter on filings but not empty — a claim-by-claim read of what exists there shows what a defensible new filing would need to avoid.
Explore white space in EurekaTrack the leading assignees' newest filings
With 84.8% of records held by the top ten, monitoring their most recent publications is the fastest way to see where the core claim space is still moving.
Set up assignee tracking in EurekaStress-test a draft claim against the most-cited records
The five most-cited records in this dataset define much of the prior art a new gate dielectric claim will be measured against; running a draft claim through them early avoids costly rework later.
Run a claim check in EurekaCommon questions on GAA gate dielectric patents
The assignee ranking covers 27 companies drawn from 92 records, and it is led by a single filer with 33 records — well ahead of the rest of the field. The top five assignees together hold 66.3% of all 92 records, and the top ten extend that to 84.8%, so this is a concentrated field rather than a fragmented one. The leaders are a mix of large integrated device manufacturers and public research institutes, reflecting how GAA gate dielectric work spans both commercial process development and academic materials research.
Filings rose from 7 in 2017 to a peak of 14 in 2019, then settled lower. The most reliable recent comparison is 2021 to 2024, which shows a -9% change — a modest pullback rather than a collapse. Counts for 2025 and 2026 look lower still, but publication typically lags filing by around 18 months, so those years are not yet complete and should not be read as a real decline.
The large majority of records, 84.8% of the 92 in scope, sit under H01L, the general semiconductor-devices classification. Nearly half, 47.8%, also carry H10D, a newer subclass that has absorbed part of the H01L docket as classification schemes have been reorganised. Smaller shares appear under B82Y (nanotechnology applications, 18.5%), H10P (10.9%), H10B (memory device manufacture, 5.4%), and single-digit shares of G03F and G11C — records often carry more than one class, so these figures add up to more than 100%.
The United States receives the largest share of filings in this dataset with 48 records, followed by China with 19. WIPO's PCT route accounts for 6, the European Patent Office 5, Taiwan 4, and the United Kingdom 3. This distribution reflects where the leading semiconductor manufacturers and research institutes in the ranking are headquartered and where they prioritise protection.
US20210083054A1, assigned to Taiwan Semiconductor Manufacturing Co., describes gate-all-around transistors built with channel members of different widths paired with gate dielectric layers of different thickness, aimed at supporting different device applications on the same structure. It is one of the more heavily cited records in this dataset, meaning later filings have repeatedly had to design around or build on its specific width-and-thickness claim structure. Anyone filing new GAA gate dielectric claims involving multi-width channel members should read its claims closely before drafting.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.