The dataset ranks 100 companies across 706 records, with the leading assignee holding 58 records against 22 at fifth place and 17 at tenth place. That gap shows a real leader but a shallow drop into the mid-field, so the next several filers are competitive rather than far behind. Across the ranked leaders as a group, the top 5 account for 29.5% of all 706 records and the top 10 account for 42.4%, leaving a substantial long tail of smaller filers active in the space.

Filing peaked in 2017 at 51 records and declined through 2024, the most recent year that can be treated as complete, with the 2021-to-2024 span showing a -35% change. The 2025 and 2026 figures in any dataset like this are still filling in, since publication typically lags actual filing by around 18 months, so they should not be read as a continuation of the decline. The honest read is a cooling from an earlier peak rather than an active, ongoing collapse.

Two IPC subclasses dominate: H03K, covering pulse technique and logic circuits, appears in 41.1% of all 706 records, and H02M, covering power conversion, appears in 36.8%. Semiconductor-device classes H01L and H10D follow at lower but still meaningful shares. Because a single record can carry multiple IPC classes, these percentages add up to more than 100%, which simply reflects that gate-timing and power-conversion claims are frequently bundled into the same filing.

US20180241391A1, assigned to Raytheon and published in 2018, describes a transformer-based gate drive circuit that generates asymmetric drive voltages using a primary winding driven by a PWM signal, a secondary winding, and two charge pumps that level-shift and then readjust the output signal. It is a specific circuit topology built around a gate drive transformer and dual charge pumps, not a generic claim over asymmetric gate drive voltages as a concept. Anyone designing a transformer-isolated gate drive with a similar dual-charge-pump readjustment stage should review its claims closely; designs using different isolation or bias-generation approaches are less likely to be affected.

Relative to the dense H03K and H02M core, branches such as negative-bias generation for paralleled devices, protection response-time measurement circuits, and gate loop inductance compensation networks show comparatively thin filing density in this dataset. That does not guarantee an open field — thin density can also mean the approach is less commercially useful — but it does mean fewer competing claims to design around. A targeted prior-art search in these specific sub-areas is a reasonable first step before committing R&D budget.