Within this dataset, the most-cited record covers CPU/GPU DCVS co-optimization for reducing power consumption in graphics frame processing, cited 80 times, well ahead of the next tier of records covering scheduling for deterministic latency and idle processing device power states. Advanced Micro Devices and its co-filers also appear repeatedly among the densest co-assignee pairs, suggesting a cluster of related SIMD and clock-gating claims from that lineage. Citation counts inside a fixed corpus tend to favour older filings that have had more years to accumulate references, so treat this as a measure of drafting influence rather than a ranking of current market strength.

The dataset shows filing peaking at 6 in 2017 and dropping toward 3 by the 2022 midpoint, with no filings recorded for any tracked assignee in the most recent year. Part of that tail-end drop is a reporting artefact: publication typically lags filing by around 18 months, so the newest years always look thinner than they will eventually be once records catch up. But the decline from 2017 through the mid-2020s is too broad to explain by lag alone, and more plausibly reflects the core clock-gating and DVFS techniques becoming settled architecture rather than an active area of new claims.

Clock gating claims typically cover shutting off the clock signal to unused logic blocks — such as individual SIMD units in a shader complex — to cut switching power without changing supply voltage. Dynamic voltage scaling (DVS or DVFS) claims instead cover adjusting supply voltage and frequency together based on workload demand, often coordinated across CPU and GPU. Several of the most-cited records in this dataset, including the top DCVS co-optimization filing, combine both mechanisms in a single claim set, which is worth checking before assuming a filing touches only one technique.

In this corpus, G06F (electric digital data processing generally) and G06T (image data processing and generation) dominate, together covering the large majority of the 63 tracked families, with G06F alone present in 57 of them. Secondary classes such as G06N (AI-based computing), H03M (coding), H04W (wireless networks), G06K (data recognition) and G09G (display control) each appear in only one or two records. That skew suggests most drafting attorneys frame GPU power claims through a digital-processing or graphics-pipeline lens even when the underlying mechanism could support a different classification.

The thinnest coverage sits in classes adjacent to the core G06F/G06T cluster: AI-model-driven power scheduling under G06N, display-controller-level power gating under G09G, coding-layer efficiency for GPU data paths under H03M, and wireless-offload power coordination under H04W each have only one or two records in this dataset. That thin coverage does not guarantee freedom to operate, since these techniques may be claimed elsewhere under different classification, but it does flag areas where a targeted search is more likely to surface open claim space than in the crowded core classes.