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The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →Filing growth compares 2021 (10 records) with 2024 (9) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.
This landscape tracks 169 patent families filed between 2015 and mid-2026 at the intersection of GPU architecture and memory integration — claims combining GPGPU or graphics-processing-unit structures with HBM integration, unified memory, on-package memory or general memory-integration language, classified under G06F13/16, H01L25/065 and G06F12. The search string requires both a GPU-architecture term and a memory-integration term to co-occur in title or claims, which narrows the corpus to filings that treat memory placement as a core architectural decision rather than a passing implementation detail.
Because publication typically lags filing by around 18 months, the 2025 and 2026 figures in any trend line understate actual filing activity; treat the most recent one to two years as a floor, not a ceiling.
Two views of the same 169 families: how filing volume moved year over year, and which IPC subclasses the claims actually sit in.
Volume moved from 11 families in 2017 to a peak of 37 in 2020, then dropped to a midpoint of 6 in 2022 before the partial 2026 count of 2. That shape reads as a technology that had its land-grab moment around 2019-2020 and has since consolidated around fewer, more defensive filings rather than continuing to expand.
169 records sit in G06F (electric digital data processing, the base classification for the search itself), but 112 also carry G06T (image data processing and generation) and 40 carry G06N (AI-model computing). The H03M, H04N, G09G, G11B and H04L counts are small by comparison, which means memory-integration claims here are overwhelmingly framed around graphics or AI workloads rather than generic storage or transmission architectures.
Shares are the percentage of the 169 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
This page is one run against one query. Ask Eureka your own question about gpu architecture memory integration and every answer comes back with the patent numbers behind it.
Try EurekaThe filing describes unified virtual addressing across GPU and CPU: an approach that combines OS-level allocation on the CPU with GPU driver mappings so a single virtual address space spans both processors, and specifically ensures a GPU-issued VA pointer cannot collide with a CPU pointer returned by standard OS allocation calls such as malloc.Filed 2015, ahead of the 2020 peak in this corpus — an early claim on unified addressing that predates most of the later filing wave.
View full filing| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20040160446A1 | Multithreaded kernel for graphics processing unit | 177 |
| 2 | US20120075319A1 | Hierarchical Memory Addressing | 85 |
| 3 | US20210150663A1 | Graphics processing unit processing and caching improvements | 69 |
| 4 | US20220066931A1 | Dynamic memory reconfiguration | 67 |
| 5 | US20210149763A1 | Systems and methods for error detection and control for embedded memory and compute elements | 57 |
| 6 | US20220122215A1 | Graphics processor operation scheduling for deterministic latency | 54 |
| 7 | WO2020190801A1 | Graphics processor operation scheduling for deterministic latency | 54 |
| 8 | US20220114096A1 | Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Provi… | 51 |
| 9 | US20210133123A1 | Techniques for an efficient fabric attached memory | 51 |
| 10 | US20180285264A1 | Preemptive cache management policies for processing units | 50 |
Citation counts inside this corpus favour older filings that have had more years to accumulate references; treat them as a measure of influence on later filers, not as a signal of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →Three read-outs from the trend, classification and citation data, framed around what they change for someone deciding where to file next.
Filings climbed from 11 in 2017 to a peak of 37 in 2020 and then fell sharply, sitting at 6 by the 2022 midpoint. A new entrant filing broad unified-memory or on-package-memory claims today is filing into a branch that has already been staked out rather than one still being defined.
Two-thirds of the corpus carries a G06T image-processing classification alongside the memory-integration terms, and 40 records also touch G06N AI-model computing. Claim drafting that frames memory integration purely as a storage-architecture problem, without tying it to a graphics or inference workload, sits outside where most of this art has actually been written.
United States receiving-office filings (112) outnumber the next largest office, EPO (16), by a wide margin, with WIPO, China, Germany and Japan each in single or low double digits. Freedom-to-operate work on this branch can prioritise US prosecution history and litigation records before expanding the search.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gpu architecture memory integration, with the prior art for and against each one.
Assignee activity in this corpus is led by a small cluster of large semiconductor and platform companies, with named inventors recurring as co-assignees on a subset of filings.
NVIDIA recorded 1 family in the latest year against 0% year-over-year change, while Intel's latest-year count fell -100% YoY to zero. Microsoft and AMD (Advanced Micro Devices (AMD)) both show zero latest-year filings in this corpus.
Only 10 co-assignee pairs appear across the corpus, and the strongest three all pair NVIDIA with individual named inventors at 3 shared filings each. This points to internal inventor teams filing jointly under one corporate assignee rather than cross-company joint filings.
NVIDIA's unified virtual addressing filing dates to 2015, five years ahead of the corpus's filing peak, suggesting foundational unified-memory claim territory was staked early and the 2018-2021 wave built on top of it rather than opening new ground.
| Assignee | Recent year | YoY |
|---|---|---|
| NVIDIA Corporation | 1 | 0% |
| Intel Corporation | 0 | -100% |
| Microsoft Corporation | 0 | — |
| Advanced Micro Devices (AMD) | 0 | — |
| RAO JAYANTH N | 0 | — |
| VENKATARAMAN VYAS | 0 | — |
| SWOBODA DWAYNE | 0 | — |
| SUNDARESAN MURALI | 0 | — |
The filing and classification data point to specific next steps depending on whether the goal is freedom-to-operate, portfolio strategy or competitive tracking.
Since most filings tie memory integration to image-processing classification, a claim chart that isolates memory-only limitations from graphics-pipeline limitations will show more clearly what is actually novel in a new filing.
Explore claim charting in EurekaWith co-assignee pairs concentrated around a small set of named inventors, monitoring those individuals' continued output is a more direct signal of near-term activity than watching the corporate assignee alone.
Set up inventor tracking in EurekaThe apparent falloff after 2020 partly reflects publication lag; re-running this search after the next data refresh will confirm whether filing has genuinely slowed or is still being reported.
Refresh this landscape in EurekaIn this dataset it means filings that combine GPU or GPGPU architecture language with memory-integration terms such as HBM integration, unified memory, or on-package memory, classified under G06F13/16, H01L25/065 or G06F12. That combination requires the claim to treat memory placement or addressing as a core architectural element rather than a downstream implementation choice. Filings that mention memory only in passing, without tying it to GPU structure, fall outside this corpus.
The corpus shows filings rising from 11 in 2017 to a peak of 37 in 2020, then falling to 6 by the 2022 midpoint. This pattern is typical of a claim space that was actively contested during a specific hardware generation and has since settled, with fewer parties filing broad foundational claims and more filing narrower, defensive ones. Publication lag also means the 2025-2026 figures are undercounted and should not yet be read as confirmation of continued decline.
NVIDIA shows the most recent-year filing activity in this corpus, holding steady with 0% year-over-year change, while Intel's latest-year activity dropped -100% YoY to zero. Microsoft and AMD both show zero filings in the latest year tracked. Co-assignee data also shows NVIDIA's strongest collaborative pairs are with individual named inventors rather than other companies, suggesting concentrated in-house inventor teams.
Sub-areas with thin representation relative to the core unified-memory and HBM-integration claims include dynamic memory reconfiguration for mixed inference and graphics workloads, error detection in embedded compute-adjacent memory, and cross-die HBM stacking address translation. These sit adjacent to the most-cited records in the corpus but have not attracted the same filing density, which is worth checking before assuming a claim direction is already crowded. A prior-art search focused specifically on these narrower branches is more useful than a broad unified-memory search at this stage.
Not necessarily. Citation counts inside a fixed corpus accumulate over time, so older filings such as the 2004-priority multithreaded-kernel record naturally collect more citations simply by having been available longer for later filers to reference. A high count signals influence on subsequent filings, not current commercial relevance or enforceability. Recent filings with few citations may still be more relevant to a present-day freedom-to-operate question.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.