https://www.patsnap.com/resources/blog/rd-blog/gpu-architecture-memory-integration-patent-landscape/ · Patsnap · data cut-off 2026-07-31 · downloaded from the live page
Computing & AI Hardware · Patent Landscape
GPU architecture memory integration patents: who is filing, and where the claim space is still open
  • Filing peaked in 2020 at 37 families, then declined through a 2022 midpoint of just 6 — this branch is past its filing peak, not accelerating toward one.
  • 112 of 169 records classify under G06T, meaning most filings tie memory integration claims directly to graphics/image pipeline processing rather than to memory architecture alone.
  • United States receiving-office filings outnumber Europe, WIPO, China, Germany and Japan combined, concentrating enforceable exposure in a single jurisdiction.
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169
Published Records
-10%
Filing Growth 2021→2024
US
Leading Jurisdiction
36
Active Filers Ranked

Filing growth compares 2021 (10 records) with 2024 (9) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field.

Published byPatsnap Research··7 min readSourced from Patsnap Eureka
Overview

What this dataset covers

This landscape tracks 169 patent families filed between 2015 and mid-2026 at the intersection of GPU architecture and memory integration — claims combining GPGPU or graphics-processing-unit structures with HBM integration, unified memory, on-package memory or general memory-integration language, classified under G06F13/16, H01L25/065 and G06F12. The search string requires both a GPU-architecture term and a memory-integration term to co-occur in title or claims, which narrows the corpus to filings that treat memory placement as a core architectural decision rather than a passing implementation detail.

Because publication typically lags filing by around 18 months, the 2025 and 2026 figures in any trend line understate actual filing activity; treat the most recent one to two years as a floor, not a ceiling.

Filing activity, 2015-2026
  1. 1INTEL CORP113
  2. 2NVIDIA CORP33
  3. 3MICROSOFT TECHNOLOGY LICENSING LLC12
  4. 4ADVANCED MICRO DEVICES INC4
  5. 5DUNNING LUCIEN3
  6. 6SHUGLA NIKITA3
  7. 7PERELYGIN KYRYLO3
  8. 8DOUILLET ALBAN3
  9. 9HAIRGROVE MARK3
  10. 10FONTAINE DAVID3
Source: Patsnap Eureka. Assignee ranking and totals. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
The data

Filing trend and technology composition

Two views of the same 169 families: how filing volume moved year over year, and which IPC subclasses the claims actually sit in.

Filings rose to a 2020 peak, then fell back

Volume moved from 11 families in 2017 to a peak of 37 in 2020, then dropped to a midpoint of 6 in 2022 before the partial 2026 count of 2. That shape reads as a technology that had its land-grab moment around 2019-2020 and has since consolidated around fewer, more defensive filings rather than continuing to expand.

Filings rose to a 2020 peak, then fell back010203040112017201820193720202021202220232024202522026Most recent year is partial — publication lag means later filings are not yet visible.

G06T dominance signals graphics-pipeline framing

169 records sit in G06F (electric digital data processing, the base classification for the search itself), but 112 also carry G06T (image data processing and generation) and 40 carry G06N (AI-model computing). The H03M, H04N, G09G, G11B and H04L counts are small by comparison, which means memory-integration claims here are overwhelmingly framed around graphics or AI workloads rather than generic storage or transmission architectures.

G06T dominance signals graphics-pipeline framingG06F · Electric digital data processi…169100.0%G06T · Image data processing & genera…11266.3%G06N · Computing based on AI models4023.7%H03M · Coding & code conversion1810.7%H04N · Pictorial communication (video…63.6%G09G · Display control circuits42.4%G11B · Information storage (magnetic/…21.2%H04L · Digital information transmissi…21.2%

Shares are the percentage of the 169 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.

Source: Patsnap Eureka. Filing trend and technology composition. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.

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Key patents

The most-cited records in this corpus

Representative filing
WO2015108708A32015-10-08

WO2015108708A3 — Unified memory systems and methods (NVIDIA CORPORATION, 2015-10-08)

NVIDIA CORPORATION

The filing describes unified virtual addressing across GPU and CPU: an approach that combines OS-level allocation on the CPU with GPU driver mappings so a single virtual address space spans both processors, and specifically ensures a GPU-issued VA pointer cannot collide with a CPU pointer returned by standard OS allocation calls such as malloc.Filed 2015, ahead of the 2020 peak in this corpus — an early claim on unified addressing that predates most of the later filing wave.

View full filing
Highest-citation filings
#Publication no.Patent titleCitations
1US20040160446A1Multithreaded kernel for graphics processing unit177
2US20120075319A1Hierarchical Memory Addressing85
3US20210150663A1Graphics processing unit processing and caching improvements69
4US20220066931A1Dynamic memory reconfiguration67
5US20210149763A1Systems and methods for error detection and control for embedded memory and compute elements57
6US20220122215A1Graphics processor operation scheduling for deterministic latency54
7WO2020190801A1Graphics processor operation scheduling for deterministic latency54
8US20220114096A1Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Provi…51
9US20210133123A1Techniques for an efficient fabric attached memory51
10US20180285264A1Preemptive cache management policies for processing units50

Citation counts inside this corpus favour older filings that have had more years to accumulate references; treat them as a measure of influence on later filers, not as a signal of current commercial relevance.

Each row carries its publication number; clicking a row searches Eureka by that number.

Source: Patsnap Eureka. Citation counts and representative records. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
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Insights

What the numbers mean for a filing decision

Three read-outs from the trend, classification and citation data, framed around what they change for someone deciding where to file next.

Filing momentum
37 → 6
peak year 2020 vs. 2022 midpoint

The land-grab phase has passed

Filings climbed from 11 in 2017 to a peak of 37 in 2020 and then fell sharply, sitting at 6 by the 2022 midpoint. A new entrant filing broad unified-memory or on-package-memory claims today is filing into a branch that has already been staked out rather than one still being defined.

Source: filing-year trend, 2017-2026
Classification concentration
112 of 169
records also classified G06T

Claims are graphics-pipeline-shaped, not generic memory claims

Two-thirds of the corpus carries a G06T image-processing classification alongside the memory-integration terms, and 40 records also touch G06N AI-model computing. Claim drafting that frames memory integration purely as a storage-architecture problem, without tying it to a graphics or inference workload, sits outside where most of this art has actually been written.

Source: IPC subclass composition
Jurisdiction spread
112 US filings
of 169 total records

Enforcement exposure concentrates in the US

United States receiving-office filings (112) outnumber the next largest office, EPO (16), by a wide margin, with WIPO, China, Germany and Japan each in single or low double digits. Freedom-to-operate work on this branch can prioritise US prosecution history and litigation records before expanding the search.

Source: receiving-office counts
Eureka AI Agent
Looking for what nobody has claimed yet?

Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to gpu architecture memory integration, with the prior art for and against each one.

Find the white space →
Source: Patsnap Eureka. Co-assignee relationships and derived observations. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
Players

Who is filing, and where they collaborate

Assignee activity in this corpus is led by a small cluster of large semiconductor and platform companies, with named inventors recurring as co-assignees on a subset of filings.

Recent momentum
0% YoY
NVIDIA, latest year

NVIDIA holds the most recent-year activity

NVIDIA recorded 1 family in the latest year against 0% year-over-year change, while Intel's latest-year count fell -100% YoY to zero. Microsoft and AMD (Advanced Micro Devices (AMD)) both show zero latest-year filings in this corpus.

Source: recent-year momentum by assignee
Co-assignee density
10 pairs
co-assignee relationships identified

Collaboration is concentrated, not broad

Only 10 co-assignee pairs appear across the corpus, and the strongest three all pair NVIDIA with individual named inventors at 3 shared filings each. This points to internal inventor teams filing jointly under one corporate assignee rather than cross-company joint filings.

Source: co-assignee pair counts
Representative filing
2015-10-08
WO2015108708A3 filing date

Early unified-memory claims predate the 2020 peak

NVIDIA's unified virtual addressing filing dates to 2015, five years ahead of the corpus's filing peak, suggesting foundational unified-memory claim territory was staked early and the 2018-2021 wave built on top of it rather than opening new ground.

Source: representative record
🔍
Under-claimed sub-areas worth checking before filing
Branches with thin representation in this corpus relative to the core unified-memory and HBM-integration claims.
Dynamic memory reconfiguration for mixed inference/graphics loadsError detection in embedded compute-adjacent memoryCross-die HBM stacking address translationOn-package memory power-state coordinationMulti-GPU unified address space fabric
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Recent-year momentum by assignee
AssigneeRecent yearYoY
NVIDIA Corporation10%
Intel Corporation0-100%
Microsoft Corporation0
Advanced Micro Devices (AMD)0
RAO JAYANTH N0
VENKATARAMAN VYAS0
SWOBODA DWAYNE0
SUNDARESAN MURALI0
Source: Patsnap Eureka. Assignee-level momentum. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
What's next

Where to take this analysis

The filing and classification data point to specific next steps depending on whether the goal is freedom-to-operate, portfolio strategy or competitive tracking.

Map claims against the G06T overlap

Since most filings tie memory integration to image-processing classification, a claim chart that isolates memory-only limitations from graphics-pipeline limitations will show more clearly what is actually novel in a new filing.

Explore claim charting in Eureka

Track NVIDIA's inventor-level filing pattern

With co-assignee pairs concentrated around a small set of named inventors, monitoring those individuals' continued output is a more direct signal of near-term activity than watching the corporate assignee alone.

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Verify the 2025-2026 dip before concluding decline

The apparent falloff after 2020 partly reflects publication lag; re-running this search after the next data refresh will confirm whether filing has genuinely slowed or is still being reported.

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Source: Patsnap Eureka. Forward-looking reading of the same dataset. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP
FAQ

Common questions on this landscape

Answers are grounded in the same dataset. Derived from a Patsnap search on GPU Architecture Memory Integration covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish.Run this in Eureka MCP

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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.

Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.

Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.

Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.