Graph Level Optimization and Memory Planning Patents
Concentrated at the top. The leading assignee alone accounts for 21 of 125 records, and the top 5 combined hold 48.0% of all 125 records in scope. Annual filings rose from 7 in 2017 to a peak of 27 in 2023, then eased to 8 by 2024, a -20% change from 2021's 10. 2025 and 2026 figures are still filling in as publications catch up with filing dates, so treat the latest two bars as provisional rather than a real decline.
- 1NVIDIA CORP21
- 2MICROSOFT TECHNOLOGY LICENSING LLC14
- 3SAMBANOVA SYSTEMS INC9
- 4CHINA MOBILE COMM GRP CO LTD8
- 5CHINA MOBILE COMM LTD RES INST8
See the full graph level optimization and memory planning analysis in Eureka
- The complete ranking, not just the top five
- Every IPC branch with its share of the corpus
- The most-cited records, and where claim space is still thin
Common questions about this landscape
Who are the leading patent filers in graph-level optimization and memory planning?
One assignee leads clearly with 21 of the 125 records in this dataset, more than double the fifth-place count of 8. The top 5 assignees combined hold 48.0% of all records, and the top 10 combined reach 73.6%. Beyond that, the ranking of 39 companies thins into a long tail of entrants with just a handful of filings each, so the field has a clear leader but is far from closed.
Is patent filing in this area growing or slowing down?
Filings rose from 7 in 2017 to a peak of 27 in 2023, then eased to 8 by 2024 -- a -20% change from 2021's 10-filing level. That looks like a cooling after a burst rather than a collapse, since the underlying compiler and runtime techniques are still being actively claimed. Figures for 2025 and 2026 are still provisional because publication typically lags filing by around 18 months, so the true recent trend is likely stronger than the raw numbers currently show.
Where should a new filing avoid dense prior art?
The densest claim territory sits in core buffer-reuse, peak-memory reduction and memory-allocator techniques tied to G06F and G06N classifications, which together cover the majority of the 125 records. Under-claimed branches include recomputation-versus-storage tradeoff scheduling, cross-accelerator partition dependency resolution, and dynamic constant-folding at runtime -- these show thinner filing density and are worth a focused freedom-to-operate check rather than an assumption of crowding. High density in the core does not mean the technology is mature, only that the claim space there is occupied.
Disclaimer. This analysis is based on Patsnap Eureka data drawn from a limited snapshot of global patent records and is provided for general information and reference only. Patent data carries inherent limitations — recent filings are under-counted because of publication lag, counts may be on a record or family basis, classification and applicant-name data may contain errors or duplicates, and the underlying search query defines the scope shown — so the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing here is an exhaustive prior-art, novelty, freedom-to-operate or validity search, nor does it constitute legal, financial or professional advice, and it should not be relied upon as such. Verify independently and review with qualified patent and legal professionals before acting on it.
Method: Filing trend and technology composition. Derived from a Patsnap search on Graph Level Optimization and Memory Planning covering 2015–2026, data cut-off 2026-07-31. Counts reflect published records only and shift as new filings publish. Every share divides by all records in scope. Data: Patsnap Eureka. See the full landscape report.