High Bandwidth Memory Patents: Top Companies & Trends 2026
- Filing peaked in 2024 at 30 records after a flat run through the early 2020s, with the most recent partial year understating true activity given typical publication lag.
- H01L dominates the IPC mix with 58 of 92 records touching semiconductor device structure, well ahead of G06F (36) and G11C (34) — the contest is over die and package architecture, not just memory logic.
- Co-filing is almost nonexistent only two co-assignee pairs appear across 92 families, meaning most HBM integration claims are filed solo rather than through joint ventures or foundry partnerships.
What this landscape covers
High Bandwidth Memory integration sits at the intersection of memory architecture and advanced packaging: stacking DRAM dies on a base die through TSV (through-silicon-via) connections, then routing that stack to a processor via a silicon interposer. The claims in this dataset cluster around three practical problems — getting signals through the stack reliably, keeping the stack cool under bandwidth-per-watt pressure, and routing the interposer without blowing the package footprint. This is not a general memory landscape; the search string ties IPC codes for semiconductor devices, digital processing and static memories to the specific vocabulary of stacking and thermal dissipation.
Ninety-two published patent families are tracked here, spanning receiving offices from the US to the EPO, India, China, South Korea and the WIPO PCT route. The US carries the largest share by a wide margin, consistent with HBM's origin in US-based GPU and memory supply chains, but the presence of India and China filings signals that downstream integrators are staking claims too.
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Filing trends and technology composition
Two views of the same 92 families: how filing volume moved year over year, and which IPC subclasses carry the claim weight.
A flat-to-declining filing curve after a 2024 peak
Filings were effectively zero in 2017, climbed through the early 2020s with 2022 sitting at a midpoint of 9, then jumped to a peak of 30 in 2024. Because publication typically lags filing by around 18 months, the most recent year on this chart understates actual filing activity rather than reflecting a real slowdown.
Semiconductor device structure leads the IPC mix
H01L (semiconductor devices) appears in 58 of 92 records, more than G06F (digital data processing, 36) and G11C (static and digital memories, 34) combined with the newer H10B manufacturing subclass (26). That ordering says the harder, more contested claim space is physical: die stacking, bonding and thermal paths, not the logic that rides on top of the memory.
Shares are the percentage of the 92 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on High Bandwidth Memory Integration with Eureka
This page is one run against one query. Ask Eureka your own question about high bandwidth memory integration and every answer comes back with the patent numbers behind it.
Try EurekaThe records other filings build on
High bandwidth memory device and system device having the same
Describes a base die with a stack of memory dies connected through a plurality of through-substrate vias, where the base die carries first input buffers for channel clock, command/address and data signals, second input buffers dedicated to test signals arriving on separate bumps, and a monitoring unit sitting between the two signal paths.US10996885B2 — Samsung Electronics, granted 2021-05-04.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20190278511A1 | High bandwidth memory device and system device having the same | 34 |
| 2 | US20230081139A1 | Integrated circuit package with flipped high bandwidth memory device | 15 |
| 3 | US10203875B1 | Methods and systems for implementing high bandwidth memory command address bus training | 12 |
| 4 | US20200144189A1 | Graphics Processing Unit and High Bandwidth Memory Integration Using Integrated Interface and Silicon Interpo… | 10 |
| 5 | US20220238146A1 | High bandwidth memory system using multilevel signaling | 9 |
| 6 | US11194505B2 | High bandwidth memory device and system device having the same | 6 |
| 7 | US20210165597A1 | High bandwidth memory device and system device having the same | 6 |
| 8 | US20210165596A1 | High bandwidth memory device and system device having the same | 5 |
| 9 | US20200393997A1 | Technology to provide accurate training and per-bit deskew capability for high bandwidth memory input/output … | 4 |
| 10 | CN110265069A | 高带宽存储器设备和具有该设备的系统设备 | 4 |
Ranked by citation count within this corpus. Older records accumulate more citations by virtue of age, so treat this as a map of influence rather than of current best practice.
Patent titles are shown in the language they were filed in, not translated, so that each record stays verifiable against the original filing — a translated title will not match in Eureka or in any national register. Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers imply for a filing decision
Three patterns worth acting on before drafting a new HBM integration claim.
Activity is bunched, not steadily rising
Filings sat near zero through 2017, moved to 9 by the 2022 midpoint, then jumped to a 2024 peak. That shape looks more like a response to a specific commercial trigger — likely AI accelerator demand for bandwidth-per-watt gains — than a steadily maturing field.
The contest is over die structure, not logic
H01L outnumbers G11C and G06F individually, and H10B (memory device manufacture) adds another 26 records. Claim pressure sits on physical stacking, bonding and via structures rather than on the command/control logic layered above them.
The US is the primary battleground, but not the only one
Europe, India, China and South Korea each carry single-digit shares, and four families route through WIPO PCT. That spread means a freedom-to-operate check limited to the US will miss active filings in at least five other jurisdictions.
Almost no joint filing activity
Only two co-assignee pairs surface across 92 families, both involving the same regional group of Chinese IC design firms. Most HBM integration claims in this dataset are filed by a single assignee acting alone, not through a joint venture or cross-licensing structure.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to high bandwidth memory integration, with the prior art for and against each one.
Who holds the claim space, and where it is thin
Recent-year momentum across the major assignees in this corpus is uniformly flat: several large memory and logic firms show 0 filings in the latest year, some with a -100% year-over-year drop. That is consistent with the publication-lag effect noted above rather than an actual pullback, but it means recent competitive position cannot be read directly off the trend line.
Large players show flat recent-year filings
Samsung Electronics, Micron, Intel, Yangtze Memory, Xilinx and Google all register zero filings in the most recent year in this dataset, with some showing a -100% year-over-year change. Given the roughly 18-month publication lag, this likely reflects filings still working through the pipeline rather than a genuine slowdown in R&D.
Solo filing is the norm, not joint ventures
The only co-filing activity in this corpus links a small cluster of Chinese IC design firms across three cities. No cross-border joint filings between the major memory and logic incumbents appear in the data.
Filing strategy already spans six offices
Beyond the US, families route through the EPO, India, China, South Korea and WIPO PCT. A company entering this space needs to check prior art across all six, not just the US, before committing to a design.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. (Korea) | 0 | -100% |
| Yangtze Memory Technologies Co., Ltd. | 0 | — |
| Intel Corporation | 0 | — |
| Micron Technology, Inc. | 0 | -100% |
| Xilinx, Inc. | 0 | — |
| Google LLC | 0 | — |
| MediaTek Inc. | 0 | -100% |
| ELIYAN CORP | 0 | — |
Turning this landscape into a filing or FTO decision
The trend and assignee data point to where to look next, not to a finished answer.
Run a freedom-to-operate check across all six offices
With 55 of the tracked filings in the US but meaningful activity in Europe, India, China, South Korea and via WIPO PCT, an FTO limited to one jurisdiction will miss live claims.
Explore FTO workflows in EurekaModel the 2024 filing spike before drafting new claims
The jump to 30 filings in 2024, after a flat 2015-2022 run, suggests a specific commercial trigger worth tracing assignee-by-assignee before assuming the field is settling.
Trace assignee momentum in EurekaTest claim language against the base-die and interposer white space
Thin filing density in monitoring circuitry, multi-stack interposer routing and AI-accelerator-specific controllers suggests room for a first claim that does not collide with the dense H01L cluster.
Draft against white space in EurekaCommon questions on HBM integration patents
The dataset shows filing activity concentrated among a small group of large memory and logic firms, including Samsung Electronics, Micron, Intel, Yangtze Memory and Xilinx, alongside a long tail of smaller filers. Recent-year filings for these major assignees read as flat or zero, which most likely reflects the roughly 18-month lag between filing and publication rather than an actual pullback in R&D. Anyone assessing ownership should look at cumulative family counts rather than the latest single year.
Based on IPC classification, the bulk of filings sit in H01L (semiconductor devices, 58 of 92 records), followed by G06F (digital data processing, 36) and G11C (static and digital memories, 34). H10B, covering memory device manufacture, adds another 26. In practice this means most claims are about the physical structure of the stacked die, TSV connections and thermal paths, not about the software or command logic that runs on top of the memory.
Filings in this dataset rose from near zero in 2017 to a midpoint of 9 by 2022, then jumped to a peak of 30 in 2024. That timing lines up with the surge in AI accelerator demand for bandwidth-per-watt performance, which pushed GPU and memory makers to file more aggressively on stacking and interposer routing. Because 2025 and 2026 filings are still publishing, the true recent trend is likely higher than the chart currently shows.
Filing density is thin in a handful of adjacent branches relative to the core stacking and thermal claims: base-die monitoring circuitry, interposer routing for multi-stack packages, AI-accelerator-specific HBM controllers, and optical interconnect approaches to HBM stacks. These areas sit next to dense H01L claim territory but are not yet heavily claimed themselves, making them a reasonable place to test new claim language. A proper novelty search against the full corpus is still necessary before committing to any of them.
Very rarely, based on this corpus. Only two co-assignee pairs appear across the 92 tracked families, and both link a small cluster of Chinese IC design firms across three cities. None of the major memory or logic incumbents show joint filings with each other in this dataset, which suggests that whatever supply-chain collaboration exists on HBM integration is not being expressed through joint patent ownership.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.