Hybrid Bonding Anneal Patents: Leaders, Trends & White Space 2026
- Filing has plateaued, not accelerated. activity peaked at 684 records in 2023 and the 2017-to-2022 midpoint trend shows growth is flat to declining, not a rising curve.
- The field is not consolidated. the ranked leader holds 1,495 records but the top 10 combined account for only 11.6% of all 83,905 records in scope — a long tail dominates.
- Momentum is reversing at several major filers. large assignees show sharp year-on-year declines in the latest year, including drops of 90% or more, consistent with a maturing claim landscape.
What this landscape covers
Hybrid bonding surface preparation and anneal spans the copper-to-copper and copper-to-dielectric interface work that determines whether a direct bond survives thermal cycling: surface roughness control, dishing control, anneal temperature profiles, copper expansion management, particle-induced void avoidance, and overlay accuracy at wafer and die scale. The dataset pulls 83,905 published records from 2015 through the 2026-07-31 cut-off, built from a search across both the bonding chemistry (copper, dielectric hybrid bond) and the process-control terms that define whether a bond is manufacturable.
Publication lags filing by roughly 18 months, so the most recent filing year in any trend undercounts what has actually been filed. Treat the last one to two years of any chart as a floor, not a ceiling.
Filing trend and technology composition
Two views of the same 83,905 records: how filing volume has moved year over year, and which IPC subclasses carry the claim density.
Filing trend, 2017–2026
Annual filings rose from 556 in 2017 to a peak of 684 in 2023, with the 2022 midpoint at 683 records. The curve is flat across the middle years rather than climbing steadily, and 2026 figures (26 so far) are still incomplete because of publication lag.
IPC subclass distribution
H01L (semiconductor devices) covers 12.2% of the 83,905 records, well ahead of every other subclass. Electroplating (C25D), printed circuits (H05K), and the wafer-level packaging classes H10W and H10P each sit in the 2.8%–3.2% range, with alloys (C22C), surface coating (C23C) and layered products (B32B) trailing below 2.5%. Because a record can carry more than one IPC class, these shares are read against the full record total and are expected to sum past 100%.
Shares are the percentage of the 83,905 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Hybrid Bonding Surface Preparation and Anneal with Eureka
This page is one run against one query. Ask Eureka your own question about hybrid bonding surface preparation and anneal and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative filing and most-cited prior art
Die to wafer direct hybrid bonding method
A die to wafer direct hybrid bonding method includes providing at least one die comprising a first copper pad and a first silicon oxide layer, providing a wafer comprising a second copper pad and a second silicon oxide layer, and handling the die so as to position the face of the die facing the zone for receiving the die on the wafer, by aligning the first and second pads. At least one water drop is deposited in the zone for receiving the die and/or on the face of the die. Pressure on the die is applied to form, from the water drop, a water film between the face and the zone for receiving the die.Filed by Commissariat a l'Energie Atomique et aux Energies Alternatives, published 2026-04-23. The water-film alignment step is a specific mechanical answer to overlay accuracy at die-to-wafer scale.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6294274B1 | Oxide thin film | 4,358 |
| 2 | US9000584B2 | Packaged semiconductor device with a molding compound and a method of forming the same | 1,042 |
| 3 | US5695810A | Use of cobalt tungsten phosphide as a barrier material for copper metallization | 893 |
| 4 | US7157787B2 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | 877 |
| 5 | US5674787A | Selective electroless copper deposited interconnect plugs for ULSI applications | 864 |
| 6 | US6050506A | Pattern of apertures in a showerhead for chemical vapor deposition | 722 |
| 7 | US20130168848A1 | Packaged semiconductor device and method of packaging the semiconductor device | 645 |
| 8 | US20020064592A1 | Electroless method of seed layer depostion, repair, and fabrication of Cu interconnects | 619 |
| 9 | US5891513A | Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications | 587 |
| 10 | US6762076B2 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices | 584 |
Citation counts favour older records simply because they have had more time to accumulate citations inside this corpus — read them as a signal of influence, not of current relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
Put your own technology through the same analysis
Eureka on the web
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →MCP server & REST API
When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →What the numbers mean for a filing decision
Three patterns stand out once the concentration, trend and composition figures are read together.
No single filer controls the space
The ranked leader holds 1,495 records, but the top five assignees together account for only 7.1% of all 83,905 records in scope, and the top ten reach just 11.6%. That is a long tail of filers rather than a field owned by two or three players, which changes freedom-to-operate work from 'clear the leader' to 'clear a broad field'.
Filing has plateaued since the early 2020s
Volume grew from 556 records in 2017 to a peak of 684 in 2023, but the 2022 midpoint of 683 sits almost level with that peak — the growth curve is flat rather than compounding. Combined with publication lag on the last two years, this looks like a technology settling into its claim boundaries rather than one still expanding.
Claim density concentrates in device architecture, not materials
H01L carries far more weight than any other subclass, while the materials- and process-adjacent classes (C22C alloys, C23C coating, B32B laminates) each sit under 2.5%. That gap suggests device-level integration claims are the crowded ground, while surface-chemistry and materials-science routes to the same bonding outcomes remain comparatively lighter.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to hybrid bonding surface preparation and anneal, with the prior art for and against each one.
| Assignee | Co-assignee | Shared families |
|---|---|---|
| Mitsubishi Materials Corp | Mitsubishi Shindoh Co Ltd | 40 |
| International Business Machines Corporation | Infineon Technologies North America Corp | 17 |
| Mitsubishi Materials Corp | CTA Technology Sole Proprietorship Ltd | 13 |
| Texas Instruments Inc | Texas Instruments Japan Ltd | 9 |
| International Business Machines Corporation | Infineon Technologies AG | 8 |
| International Business Machines Corporation | IBM UNITED KINGDOM LTD INTELLECTUAL PROPERTY DEPARTMENT | 8 |
| International Business Machines Corporation | STMICROELECTRONICS INC | 7 |
| Applied Materials Inc | CHUNG HUA | 7 |
Recent-year filings dropped sharply across several major assignees, with declines of 56% to 100% year-on-year — a sign the largest filers are pulling back rather than pushing further into this claim space.
Who is filing, and where the activity is thinning
The ranking spans 100 companies counted by records, from a leader at 1,495 down through a long tail — not a top-50 or top-100 cut, but the whole list the data endpoint returns.
A clear leader without a monopoly
The top-ranked assignee's 1,495 records place it well ahead of fifth place at 990, but that gap closes quickly further down the list — tenth place holds 659, and the top ten combined still only reach 11.6% of all records in scope.
Large filers are stepping back
Multiple assignees that filed steadily in prior years show year-on-year drops of 90% or more in the latest year, including at least one large filer at zero. This is consistent with a field where core claim territory has already been staked out.
US and Europe anchor the filing map
The United States receives more filings than any other office in this dataset (11,459), with Europe (EPO) at 3,425 and WIPO/PCT filings at 1,817. United Kingdom, Singapore and Canada each register meaningfully lower but non-trivial volumes.
| Assignee | Recent year | YoY |
|---|---|---|
| Intel Corp | 4 | -56% |
| Applied Materials Inc | 2 | -90% |
| Taiwan Semiconductor Manufacturing Co Ltd | 1 | -94% |
| Micron Technology Inc | 1 | -95% |
| Texas Instruments Inc | 1 | -75% |
| International Business Machines Corporation | 0 | -100% |
| JX Nippon Mining & Metals Corp | 0 | — |
| Mitsui Mining & Smelting Co Ltd | 0 | — |
Where to take this analysis
The dataset points to specific next steps depending on whether the goal is freedom-to-operate, whitespace filing, or competitor tracking.
Run a freedom-to-operate check on device-level claims
With H01L carrying 12.2% of all records, any device-integration approach to hybrid bonding is filing into the densest part of this landscape. A targeted clearance search on the specific claim elements is worth doing before committing engineering resources.
Explore in Patsnap EurekaTrack the assignees pulling back
Several large filers show year-on-year declines of 90% or more. Confirming whether that reflects a shift to trade secret protection, licensing, or genuine disengagement changes how much weight to put on their existing portfolios.
Explore in Patsnap EurekaTest claims in the lighter-density sub-areas
Materials- and process-adjacent classes such as alloys, coatings and laminates sit well below the device-architecture classes in record share. A first claim drafted around dishing control or copper expansion compensation may face less crowded prior art.
Explore in Patsnap EurekaCommon questions on this landscape
The ranked leader holds 1,495 records, with fifth place at 990 and tenth place at 659 out of the 100 companies in the ranking. However, the top five combined account for only 7.1% of the 83,905 total records in scope, and the top ten reach 11.6% — so no single company or small group controls the field. Freedom-to-operate work here needs to look well beyond the top few names because the remaining activity is spread across a long tail of filers.
Filing volume rose from 556 records in 2017 to a peak of 684 in 2023, but the 2022 midpoint of 683 sits almost level with that peak, indicating the growth curve has flattened rather than continuing to climb. Recent-year momentum data reinforces this: several major assignees show year-on-year declines of 56% to 100% in the latest year. Because publication lags filing by roughly 18 months, the very last one to two years in any trend chart will always look lower than the true filing rate, so a short-term dip should not be read as a hard stop.
H01L, the semiconductor devices classification, covers 12.2% of the 83,905 records in this dataset and is clearly the densest single subclass. Electroplating (C25D), printed circuits (H05K), and wafer-level packaging classes H10W and H10P each sit around 2.8% to 3.2%, with alloys, coatings and laminates trailing below 2.5%. Because records can carry multiple IPC classes, these percentages are read against the total record count and are expected to add up to more than 100%.
This filing, from Commissariat a l'Energie Atomique et aux Energies Alternatives and published 2026-04-23, claims a specific method of using a water film between a die and a wafer to achieve alignment before pressure bonding, targeting the overlay accuracy problem directly. Anyone developing a die-to-wafer hybrid bonding process that uses a liquid interface layer for alignment purposes should review this filing's claim scope closely rather than assume general prior art in the space covers the approach. It is a recent filing, so its full prosecution and any related family members are worth tracking as the application proceeds.
The IPC composition data shows materials- and process-adjacent classes such as alloys (C22C), surface coatings (C23C) and layered laminates (B32B) each carry under 2.5% of the 83,905 records, well below the 12.2% concentration in device-architecture claims under H01L. That gap suggests approaches built around materials science solutions to dishing control, copper expansion, or particle-induced voiding may face lighter prior art than device-integration claims. It is not proof the area is empty, only that the claim density measured here is comparatively lower, so a targeted search of that narrower slice is the right next step before drafting.
Research Hybrid Bonding Surface Preparation and Anneal in depth with Eureka
Go past this page: query the whole hybrid bonding surface preparation and anneal corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.