Hybrid Bonding Patents: Who Leads, Where the Gaps Are 2026
- Filing activity peaked in 2018 at 5 records and has since gone flat, with the 2022 midpoint at zero — a small, quiet corpus rather than a fast-growing one.
- Every recent-year assignee tracked shows zero filings in the latest year, including a -100% YoY drop for one major materials-and-equipment player, suggesting the field is between filing cycles.
- Citations concentrate on a handful of early records, led by a chip-to-chip alignment accuracy patent cited 60 times — a strong signal of foundational influence, not current activity.
What this landscape covers
This review tracks patent families matching hybrid bonding, wafer-to-wafer bonding and die-to-wafer bonding in the claims, narrowed to filings that also address copper-copper bonding, surface activation, bonding alignment, dielectric bonding or hybrid bond interface within the IPC classes covering semiconductor device assembly, wafer processing and multi-substrate stacking.
The corpus is small — 19 published records across 19 families — which makes this a niche but technically dense pocket of the semiconductor packaging space rather than a broad category. Publication lags filing by roughly 18 months, so any apparent slowdown in the most recent year understates real filing activity.
Filing trend and technology composition
Nineteen patent families sit inside this search, filed between 2015 and the mid-2026 cutoff. The trend line and IPC spread below show where the claim density actually sits, rather than where the topic name suggests it should.
A peak in 2018, then a flat line
Filings rose to 5 in 2018 from 2 in 2017, then fell back toward zero by the 2022 midpoint and have stayed low through the most recent partial year. This pattern reads as an early filing burst around a core set of bonding techniques, followed by consolidation rather than continued expansion — though the last one to two years are undercounted due to publication lag.
Concentrated in one IPC subclass
All 19 records classify under H01L (semiconductor devices), with smaller overlaps into H10P (8), B81B microstructural/MEMS devices (3) and H10W (3). The near-total overlap with H01L confirms this is squarely a semiconductor device-assembly technology, with only a modest footprint reaching into MEMS-adjacent structures.
Shares are the percentage of the 19 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Hybrid Bonding Technology Landscape with Eureka
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Try EurekaThe most-cited records in this corpus
Method for hybrid wafer-to-wafer bonding
The method bonds two silicon wafers carrying copper pattern structures: a standard copper back-end-of-line process planarizes the copper and dielectric surface, an etch step forms controlled copper recesses, a bonding metal is selectively deposited into those recesses, both the metal and the dielectric surface undergo surface activation, and the wafers are then aligned and pressed together to form the combined dielectric-and-metal bond.Filed by Shanghai IC R&D Center, published 2019-07-11.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US9466538B1 | Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process | 60 |
| 2 | US20150031189A1 | Mechanisms for cleaning substrate surface for hybrid bonding | 28 |
| 3 | US20190214257A1 | Method for hybrid wafer-to-wafer bonding | 20 |
| 4 | US10796913B2 | Method for hybrid wafer-to-wafer bonding | 20 |
| 5 | US20150243537A1 | Mechanisms for cleaning substrate surface for hybrid bonding | 8 |
| 6 | US10727097B2 | Mechanisms for cleaning substrate surface for hybrid bonding | 4 |
| 7 | WO2018211447A1 | Hybrid bonding method for semiconductor wafers and related three-dimensional integrated device | 2 |
| 8 | EP2351076B1 | Method and apparatus for wafer bonding with enhanced wafer mating | 2 |
| 9 | US11127776B2 | Hybrid bonding method for semiconductor wafers and related three-dimensional integrated device | 1 |
Citation counts reflect influence within the searched corpus and skew toward older filings; they are not a measure of current commercial relevance.
Publication numbers are shown where the record carries one (9 of 9 rows); clicking a row searches Eureka by that number.
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Three patterns stand out once family counts, citation concentration and IPC spread are read together.
The core techniques were staked out early
The bulk of activity clusters around 2017-2018, covering copper-copper bonding, surface activation and alignment accuracy. The drop to zero by 2022 suggests the foundational claim space filled quickly rather than expanding steadily.
Influence sits with a small set of early patents
One chip-to-chip alignment accuracy patent and two substrate-cleaning patents account for most of the citation weight in this corpus. Later filings on hybrid wafer-to-wafer bonding are cited far less, which is expected given their more recent publication dates.
Almost no diversification outside core semiconductor assembly
MEMS-adjacent filings (B81B) and the H10P/H10W overlaps are a minority presence. This is a tightly scoped technology area rather than one that has branched into adjacent device classes.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to hybrid bonding technology landscape, with the prior art for and against each one.
Who holds the claims, and where the gate sits
Recent-year momentum across the tracked assignees is uniformly flat: every one shows zero filings in the latest year, including a materials-and-equipment player down -100% year-on-year. That flatness, combined with a small 19-family corpus, means the field is gateable by a handful of foundational filings rather than defended by volume.
Large fabs hold early alignment and cleaning art
The most-cited records in this corpus, covering chip-to-chip alignment accuracy and substrate surface cleaning for hybrid bonding, sit with large integrated device makers and foundry-adjacent filers whose activity has since gone quiet in the tracked window.
Equipment suppliers pulled back sharply
At least one equipment-and-materials assignee shows a full year-on-year drop to zero filings, consistent with the broader flat trend rather than an isolated event.
Applied research groups hold process-integration claims
Filings such as the representative dielectric-and-copper hybrid bonding method came from applied semiconductor R&D centres rather than only from product-line assignees, indicating the process integration work is shared across research and manufacturing organisations.
| Assignee | Recent year | YoY |
|---|---|---|
| Lefondery Ltd. | 0 | — |
| SUSS MicroTec Lithography GmbH | 0 | — |
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| Applied Materials, Inc. | 0 | -100% |
| Shanghai IC R&D Center Co., Ltd. | 0 | — |
| Invensas Bonding Technologies, Inc. | 0 | — |
| Adeia Semiconductor Bonding Technologies Inc. | 0 | — |
| GlobalFoundries Inc. | 0 | — |
Where to take this analysis
The trend and assignee data point to a narrow, foundational claim set rather than a fast-moving field. Two follow-ups make sense before committing engineering or filing resources.
Check freedom-to-operate against the top-cited records
The alignment-accuracy and substrate-cleaning patents carry the heaviest citation weight in this corpus and are the most likely prior art an examiner will raise against a new hybrid bonding filing.
Run a freedom-to-operate check in EurekaTrack when filings resume
Every tracked assignee is flat at zero in the latest year. A renewed uptick from any of them is an early signal that the next packaging generation is moving from lab to filing.
Set up filing alerts in EurekaCommon questions about hybrid bonding patents
Hybrid bonding joins two wafers or a die and a wafer by simultaneously bonding a metal pattern, usually copper, and the surrounding dielectric in a single interface, rather than using solder bumps or adhesive. It requires very tight alignment between the two surfaces and a surface activation step so the dielectric bonds at low temperature before the copper interconnects fully form. This is the technique behind high-density 3D chip stacking used in advanced image sensors, memory and logic-on-logic packaging.
This corpus of 19 patent families shows activity from a mix of large integrated device makers, foundry-adjacent filers, equipment and materials suppliers, and applied semiconductor R&D centres. The most-cited records, covering chip-to-chip alignment accuracy and substrate surface cleaning, sit with early filers rather than the most recent entrants. No single assignee shows filing activity in the latest tracked year, so current leadership is better read from historical citation weight than from recent filing counts.
The filing trend in this dataset rises to a peak of 5 records in 2018 from 2 in 2017, then falls back toward zero by 2022. This pattern is typical of a technique moving through an early staking-out phase, where the foundational process steps, alignment methods and surface preparation techniques get claimed quickly by a small number of filers. It does not necessarily mean interest declined; it more likely means the core claim space filled and later work shifted to trade secret or unpublished process refinement, or has not yet published given the roughly 18-month lag between filing and publication.
Given the tight concentration of filings in copper-copper bonding and general surface activation, several adjacent branches remain thinly covered in this corpus, including low-temperature dielectric activation chemistries, post-bond misalignment correction for die-to-wafer processes, void detection at the bond interface, and bonding interfaces integrated with MEMS structures. These are technically specific gaps rather than the well-trodden core alignment and cleaning claims already held by early filers.
US20190214257A1, filed by Shanghai IC R&D Center, claims a specific sequence: planarizing a copper-and-dielectric surface via back-end-of-line processing, etching controlled copper recesses, selectively depositing a bonding metal into those recesses, activating both the metal and dielectric surfaces, then aligning and pressing the wafers together. Anyone filing a similar recessed-copper-plus-selective-deposition sequence for hybrid bonding should check their process order and materials against this claim scope. Alternatives that avoid the recess-and-selective-deposition combination, such as different surface planarization or activation sequencing, may sit outside its claims.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.