In-Line Scatterometry for CD Uniformity — PatSnap Eureka
In-Line Scatterometry for Real-Time CD Uniformity Control in Logic Fabs
How optical diffractometry, advanced process control architectures, and hierarchical CDU mapping combine to keep critical dimensions on target across high-volume logic manufacturing — drawing on 50+ patents from KLA-Tencor, ASML, AMD, and TSMC.
How Scatterometry Extracts CD Without Destroying the Wafer
Scatterometry leverages the angular or spectral signature of light diffracted from periodic on-wafer structures to infer critical dimension (CD), sidewall angle, and film thickness without physical contact or sample destruction. The technique became practical for production control as semiconductor features shrank below the wavelength of visible light, making direct optical imaging insufficient while CD-SEM throughput remained inadequate for high-volume sampling.
A foundational calibration method, patented by Advanced Micro Devices in 2003, involves measuring the CD of at least one production feature using a scatterometry tool, simultaneously measuring a set of grating structures each with a different known CD, and using those grating measurements to correct the production-feature measurement. This closes the gap between library-based model fits and actual fab process conditions, reducing systematic offset errors that would otherwise propagate into APC corrections.
ASML's differential-signal scheme adds a bias-independent reference point: periodic targets with different CD biases are illuminated, scattered radiation intensities are measured, and a differential signal is computed. The key physical insight is that this differential signal approximates zero at a 1:1 line-to-space ratio. The determined CD or exposure dose is then fed directly into the scanner APC to correct lithographic processing of subsequent substrates.
Academic validation from the Catalan Institute of Nanoscience and Nanotechnology (2020) confirmed real-time optical scatterometry measuring multiple diffraction orders from silicon gratings, with cross-referencing against FIB, SEM, and scanning stylus profilometry — validating the diffractometric measurement physics that underlies wafer-fab scatterometry.
Feedback, Feed-Forward, and Sub-Field Control for CDU
The translation of scatterometry measurements into actionable process corrections is the core value proposition of in-line metrology. Two fundamental control topologies — and increasingly granular spatial correction — define the modern APC stack.
Measurements on Processed Lots Drive Corrections to Subsequent Wafers
AMD's 2004 patent on measuring in-circuit structures — not dedicated test gratings — generates feedback signals that selectively adjust fabrication components and operating parameters. Direct in-circuit measurement eliminates the need to reserve chip real estate for dedicated test gratings, enabling control over the actual device structures that determine final chip performance.
AMD, US 2004 — in-circuit scatterometryUpstream Scatterometry Data Pre-Corrects Downstream Process Steps
AMD's 2005 reticle-level patent routes scatterometry data gathered from the reticle itself — compared against stored signature libraries — forward to control subsequent reticle etch processes. This closes an upstream control loop that prevents reticle CD errors from propagating to printed wafer CDs. The same framework was extended to concurrent CD and overlay measurement in a single metrology pass (AMD, US 2006).
AMD, US 2005 — reticle feed-forwardASML's Most Granular APC: Intra-Field Corrections Within a Single Scanner Exposure
ASML's 2022 CN patent uses measurement data from scatterometry and other tools to determine intra-field corrections to drive the lithography apparatus, with a precision metric computed when measurement data reliability is uncertain. The system continuously loops measurement data back to minimize the risk of patterning drifting outside the process window — defined as the range of dose, focus, and overlay parameters yielding a functional semiconductor device.
ASML, CN 2022 — sub-field controlTSMC's Validation Layer Prevents Runaway Correction Instability
TSMC's 2012 defense system patent establishes that overlay process value settings derived from metrology measurements are compared against a high/low specification computed from current overlay error data. The system validates that any proposed correction falls within acceptable control bounds before applying it — a guard-rail function that prevents run-away APC corrections from introducing systematic CD offsets. This is essential when scatterometry-derived corrections are applied automatically at high throughput.
TSMC, US 2012 — APC defense systemAPC Evolution and CDU Monitoring Coverage
Three decades of patent filings reveal a clear progression from single-point CD measurement to EPE-driven, probabilistic yield control — and from sparse sampling to full-wafer CDU maps.
APC Capability Evolution by Era (1989–2025)
From single-point test-grating CD in the early 2000s to sub-field EPE-driven yield control by 2022+, each era added a new measurement and correction dimension.
CDU Monitoring Approaches by Technical Theme
Patent records cluster around three primary technical axes: optical scatterometry signal acquisition, feedback/feed-forward control loops, and hybrid metrology CDU mapping.
From Sparse Sampling to Full-Wafer Die-Level CDU Maps
Achieving statistically representative CD monitoring without consuming excessive metrology tool time requires smart sampling architectures. These four approaches — from different assignees — address the throughput-precision trade-off from complementary angles.
Representative Feature Selection — LSI Logic (2004)
A cluster of CD features on the reticle is measured; the cross-chip average feature size is computed; and the CD feature whose dimension is closest to that average is selected as the standard in-line measurement target. This ensures the single measurement point used for routine production monitoring genuinely reflects the chip-wide average rather than an outlier location — correcting a systematic bias inherent in arbitrarily chosen measurement sites.
Dynamic Metrology Sampling — IBM (TW 2011)
A pre-process measurement map is generated from sparse measurements; isolated and nested structures are sampled separately; and a confidence map is computed for each die. When confidence data for one or more dies fall outside defined limits, a priority measurement position is added to the recipe — dynamically concentrating metrology effort at the wafer sites most at risk of CDU excursion.
Key Assignees and Their Innovation Focus Areas
The dataset spans more than 50 unique records across six jurisdictions. Dominant assignees cluster around distinct technical themes — from scanner-integrated scatterometry to die-level CDU monitoring.
| Assignee | Filing Volume | Jurisdictions | Primary Technical Focus | Patent Status |
|---|---|---|---|---|
| ASML Netherlands B.V. | 10+ records | US, WO, CN | Scanner-integrated scatterometry, differential CD-signal methods, sub-field correction, EPE-driven APC | Active 2016–2025 |
| Advanced Micro Devices (AMD) | 8+ records | US, WO, EP, AU | In-circuit scatterometry, concurrent CD-overlay, reticle-level feed-forward control | Foundational prior art |
| KLA-Tencor Corporation | 7+ records | US, WO, CN | Multi-modal metrology, CDU mapping (SEM+optical), 3D integration feed-forward | Active (2019, 2024) |
| Hermes Microvision Inc. | 7+ records | US | High-speed e-beam die-by-die CDU monitoring aligned to design layouts | Active 2012–2016 |
| TSMC | 2 records | US | APC defense system, CDU improvement for wafer patterned structures | 2012 |
| IBM | 2 records | TW, US | Dynamic metrology sampling, stepper-focus-monitor integration for CD accuracy | 2003–2011 |
Track Active Patents Across All Assignees in Real Time
PatSnap Eureka monitors legal status changes, new filings, and citation networks across the full CDU control IP landscape.
Seven Key Takeaways from 30 Years of Scatterometry APC Patents
The patent record distils into actionable engineering and IP intelligence. Each finding is traceable to a specific patent or literature source in the dataset.
Eliminate the Test-Grating Real-Estate Penalty
By measuring repeating in-circuit structures directly, fabs gain control over the actual device features that determine chip performance without sacrificing die area to dedicated gratings. Pioneered by AMD in US 2004, this approach is now standard practice.
AMD, US 2004Dose-Independent CD Extraction via Paired Target Comparison
ASML's method of computing differential signals from pairs of targets with different CD biases separates CD from exposure dose without needing absolute intensity calibration. The differential signal approximates zero at a 1:1 line-to-space ratio — a bias-independent reference point. Disclosed in ASML US 2016, confirmed in US 2019.
ASML, US 2016 & 2019Prevent Mask CD Errors From Printing to Wafers
Routing reticle-level scatterometry signatures into downstream etch APC closes a critical upstream control gap. AMD's 2005 patent established that scatterometry data gathered from the reticle itself — compared against stored signature libraries — can pre-correct etch processes before mask errors propagate to wafer CDs.
AMD, US 2005APC Is Evolving from CD to Edge Placement Error
ASML's 2025 US patent establishes edge-placement error (EPE) derived from image contours as a control parameter — signaling the extension of scatterometry-informed APC beyond CD to full-pattern fidelity. EPE integrates CD, overlay, and pattern fidelity as the ultimate yield-relevant quantity. Explore the full patent analytics landscape for EPE control methods.
ASML, US 2025 — active- Hierarchical CDU mapping — CD-SEM for initialization, optical metrology for coverage — optimizes the throughput-precision trade-off (KLA-Tencor, US 2019)
- Representative CD feature selection is essential for CDU monitoring validity; arbitrarily chosen sites may misrepresent chip-wide CD averages (LSI Logic, 2004)
- APC guard-rail mechanisms are required to prevent correction instability at high throughput; every correction must be validated against a specification band before application (TSMC, US 2012)
From Scatterometry Signal to Corrected Exposure: The End-to-End Control Loop
A high-volume logic fab's scatterometry APC loop spans three stages: measurement and calibration, signal processing and control decision, and correction application with guard-rail validation.
Diffract light from periodic on-wafer or in-circuit structures. Acquire angular or spectral signature. Compare against golden-wafer reference or simulation-derived intensity-gradient sensitivities (ASML, US 2016/2019). Compute differential signal for bias-independent CD extraction.
Route measurement to feedback (correct subsequent lots) or feed-forward (pre-correct downstream step). Validate proposed correction against high/low specification band — TSMC's defense system (US 2012) — before applying. Compute precision metric if measurement data reliability is uncertain (ASML, CN 2022).
Send validated correction to scanner (dose, focus, intra-field sub-field), etch tool (recipe, gas flow, temperature), or upstream reticle etch APC. For CDU mapping, generate second dense optical inspection pass guided by the SEM-initialized CDU map (KLA-Tencor, US 2019). Monitor production outcomes for closed-loop stability.
In-Line Scatterometry for CD Uniformity — Key Questions Answered
Scatterometry leverages the angular or spectral signature of light diffracted from periodic on-wafer structures to infer CD, sidewall angle, and film thickness without physical contact or sample destruction. The technique became practical for production control as semiconductor features shrank below the wavelength of visible light, making direct optical imaging insufficient while CD-SEM throughput remained inadequate for high-volume sampling.
Two fundamental control topologies are employed: feedback control, where measurements on a processed lot drive corrections to subsequent lots or wafers, and feed-forward control, where upstream measurement data are routed ahead to pre-correct a downstream process step before the wafer arrives.
A critical advantage noted in AMD's patent is that direct in-circuit measurement eliminates the need to reserve chip real estate for dedicated test gratings, enabling control over the actual device structures that determine final chip performance.
Periodic targets with different CD biases are illuminated, scattered radiation intensities are measured, and a differential signal is computed. The key physical insight is that this differential signal approximates zero at a 1:1 line-to-space ratio, providing a bias-independent reference point. The determined CD (or exposure dose) is then fed directly into the scanner APC to correct lithographic processing of subsequent substrates.
TSMC's Defense System in Advanced Process Control establishes that overlay process value settings derived from metrology measurements are compared against a high/low specification computed from current overlay error data. The system validates that any proposed correction falls within acceptable control bounds before applying it — a guard-rail function that prevents run-away APC corrections from introducing systematic CD offsets.
ASML's Method of Determining Control Parameters of a Device Manufacturing Process (US 2025) establishes edge-placement error (EPE) derived from image contours as a control parameter — signaling the extension of scatterometry-informed APC beyond CD to full-pattern fidelity. EPE is a metric that integrates CD, overlay, and pattern fidelity as the ultimate yield-relevant quantity.
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References
- Using Scatterometry to Obtain Measurements of In-Circuit Structures — Advanced Micro Devices, Inc., US 2004
- Using Scatterometry to Optimize Circuit Structure Manufacturing Processes — Advanced Micro Devices, Inc., WO 2004
- Using Scatterometry to Optimize Circuit Structure Manufacturing Processes — Advanced Micro Devices Inc., EP 2005
- Feed Forward Process Control Using Scatterometry for Reticle Fabrication — Advanced Micro Devices, Inc., US 2005
- Concurrent Measurement of Critical Dimension and Overlay in Semiconductor Manufacturing — Advanced Micro Devices, Inc., US 2006
- Method and Structure for Calibrating Scatterometry-Based Metrology Tool — Advanced Micro Devices, Inc., AU 2003
- Method for Process Optimization and Control by Comparison Between 2 or More Measured Scatterometry Signals — KLA-Tencor Corporation, 2008
- Integrated Scanning Electron Microscopy and Optical Analysis Techniques for Advanced Process Control — KLA-Tencor Corporation, US 2019 (active)
- Method of Determining Critical-Dimension-Related Properties, Inspection Apparatus and Device Manufacturing Method — ASML Netherlands B.V., US 2016 (active)
- Method of Determining Critical-Dimension-Related Properties — ASML Netherlands B.V., US 2019 (active)
- Method of Determining Control Parameters of a Device Manufacturing Process — ASML Netherlands B.V., US 2025 (active)
- Sub-Field Control of Lithographic Process and Associated Apparatus — ASML Netherlands B.V., CN 2022 (active)
- Defense System in Advanced Process Control — Taiwan Semiconductor Manufacturing Company, Ltd., US 2012
- Method and System for Measuring Critical Dimension and Monitoring Fabrication Uniformity — Hermes Microvision Inc., US 2012
- Lithography Line Width Monitor Reflecting Chip-Wide Average Feature Size — LSI Logic Corporation, 2004
- Dynamic Metrology Sampling with Wafer Uniformity Control — International Business Machines Corporation, TW 2011
- Method Using SCD to Monitor In-Line Product Focus Variation — Shanghai Huali Integrated Circuit Manufacturing Co., 2019
- Method of Determining Semiconductor Process Conditions — United Microelectronics Corporation, CN 2007 (active)
- Real-Time Optical Dimensional Metrology via Diffractometry for Nanofabrication — Catalan Institute of Nanoscience and Nanotechnology (ICN2), 2020
- Compact Optical System Based on Scatterometry for Off-Line and Real-Time Monitoring of Surface Micropatterning Processes — Technische Universität Dresden, 2023
- World Intellectual Property Organization (WIPO) — International patent database
- European Patent Office (EPO) — EP jurisdiction patent records
- SPIE Digital Library — Optical scatterometry and semiconductor metrology literature
All data and statistics on this page are sourced from the references above and from PatSnap's proprietary innovation intelligence platform.
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