In-Memory Computing Chip Architecture: 2026 Patent Landscape
In-Memory Computing Chip Architecture Patents 2026
In-memory computing has shifted from academic concept to commercial silicon, with 8 formal patent records spanning SRAM digital macros, resistive memory crossbars, and chiplet packaging architectures. A single Chinese assignee accounts for 7 of those filings, all targeting EP and US jurisdictions in 2025.
How In-Memory Computing Eliminates the Memory Wall
In-memory computing directly addresses the memory wall — the performance gap in von Neumann architectures where data must shuttle repeatedly between physically separated compute and memory units. This bottleneck is cited as the motivating constraint in over 80% of the literature sources reviewed, spanning publications from 2018 through 2026.
IMC architectures span both analog and digital computation domains, utilizing charge-based memories such as SRAM and DRAM as well as emerging devices based on electrically induced material modifications. The field branches into analog IMC (AiMC), digital IMC (DIMC), processing-in-memory (PIM), and chiplet-based IMC disaggregated via 2.5D, 3D, and fan-out packaging.
SRAM remains the dominant substrate for digital IMC due to its prevalence in logic process nodes, mature bitcell designs, and compatibility with conventional CMOS toolchains. The 28 nm Arizona State prototype integrates 108 capacitive-coupling-based IMC SRAM macros totaling 3.4 MB, achieving 4.9 TOPS and 437 TOPS/W peak efficiency with a custom SIMD ISA.
As monolithic IMC faces area, yield, and routing constraints at scale, chiplet disaggregation has emerged as the dominant scaling path. WitMem Technology filed at minimum 7 patent families in EP and US in June 2025 alone, covering dual-chip, triple-chip with DRAM, and triple-chip with NAND configurations — all carrying Chinese priority dates from December 2023.
Patent Activity by Technology Cluster and Filing Period
The IMC dataset spans 2014 to 2026, with approximately 60% of all sources concentrated in 2020–2022 and a shift toward commercial IP consolidation from 2023 onward. Four dominant technology clusters — SRAM digital IMC, resistive/NVM IMC, chiplet-based IMC, and scalable array fabric — structure the patent landscape.
Patent Records by Technology Cluster — IMC Dataset 2014–2026
Chiplet-based and SRAM digital IMC clusters jointly account for the largest share of formal patent filings, reflecting commercial consolidation around packaging and precision compute.
↗ Click bars to exploreIMC Patent Filing Activity by Period (2014–2026)
Filing and publication density surged in 2020–2022, representing approximately 60% of all retrieved results, with a second wave of commercial patent filings emerging from 2023 onward.
↗ Click bars to exploreKey IMC Application Domains Across AI, Edge, and HPC
IMC architectures are being deployed across five distinct application domains identified in the retrieved literature and patent records: AI inference, edge intelligence, high-performance computing, cryptography, and hyperdimensional computing.
AI Inference and Deep Neural Networks
The largest and most consistently cited application domain across retrieved results. The Arizona State 28 nm prototype achieves 4.9 TOPS and 437 TOPS/W benchmarked on DNN layer types including convolution, pooling, and fully connected layers. D-Matrix’s 2025 US patent explicitly targets NLP, generative AI, and agentic AI workloads via hierarchical DIMC chiplet systems.
AI InferenceEdge Intelligence and IoT Devices
A heterogeneous IMC cluster integrating 8 RISC-V cores and an analog IMC accelerator was benchmarked on battery-constrained TinyML applications (2022). A time-multiplexing CIM architecture demonstrated 18.4× energy savings over conventional analog CIM with 0.136 pJ/MAC efficiency for edge deployment, also published in 2022.
Edge IntelligenceHigh-Performance Computing and Data Centers
PIM architectures targeting graph analytics, databases, and neural network inference in server environments were benchmarked in a 2022 experimental analysis of a real processing-in-memory system. Applied Intelligence Semiconductors’ 2025 WO patent discloses a CXL-connected architecture comprising a primary chip, memory pool chip, IO complex chip, and AI tensor node chip for data center adaptability.
High-Performance ComputingCryptography and Hyperdimensional Computing
In-SRAM cryptographic hash computation for IoT security was demonstrated in a 2022 study on both SRAM and ReRAM substrates, enabling data integrity and authentication hardware via in-memory architectures. Separately, a 2022 paper demonstrated IMC for hypervector similarity search across physically distributed IMC cores, representing a non-neural-network AI application for IMC.
Security & Cognitive AIWho Holds the Core IMC Architecture IP in 2026
Among the 8 formal patent records with explicit assignee data, Hangzhou Zhicun (WitMem) Technology accounts for 7 filings targeting EP and US jurisdictions in 2025, while Princeton University holds 3 filings across WO, US, IN, and JP jurisdictions spanning 2019–2023.
IMC Patent Filings by Top Assignees (Dataset 2014–2026)
↗ Click bars to exploreHangzhou Zhicun (WitMem) Technology
WitMem Technology holds 7 patent records in this dataset, all filed in EP and US jurisdictions in June 2025, carrying Chinese priority dates from December 2023. The portfolio covers dual-chip and triple-chip CIM architectures incorporating CIM cell array chips, peripheral analog/digital circuit chips, and either DRAM or NAND flash memory tiers depending on capacity vs. latency requirements. All filings are currently pending, establishing broad coverage over multi-chip CIM packaging with heterogeneous memory tiers.
China — EP/US filingsThe Trustees of Princeton University
Princeton University holds 3 filed/granted patents in this dataset spanning WO, US, IN, and JP jurisdictions across 2019–2023. The portfolio covers configurable IMC cores interconnected by a configurable on-chip network (US 2023, pending), a reshaping buffer for massively parallel bitwise input signals with near-memory computing paths (WO 2019), and a scalable array architecture for in-memory computing (WO 2021, IN 2022). These foundational academic patents provide broad coverage over mesh-connected IMC core arrays and programmable IMC SoC fabrics.
United States — WO/US/IN/JPFour Emerging IMC Architecture Directions Identified in 2024–2026 Filings
The most recent filings from 2024 to 2026 in this dataset signal four distinct directions: heterogeneous multi-chip CIM packaging, stacked digital IMC chiplets for generative AI, topology-aware interconnect optimization, and workload-general programmable CIM fabrics.
Multi-Chip CIM Packaging with Heterogeneous Memory Tiers
WitMem Technology’s 2025 EP/US patent family introduces architectures incorporating three distinct chip types within a single CIM package: CIM cell arrays, a peripheral analog/digital circuit chip, and either a DRAM tier (US 2025) or a NAND flash tier (EP 2025), depending on the application’s capacity vs. latency requirements. The Chinese priority dates from December 2023 predate most Western commercial CIM product announcements, giving WitMem a potential first-mover IP position in multi-tier CIM packaging.
Stacked Digital IMC Chiplets for Generative AI Inference
D-Matrix Corporation’s Stacked apparatus using in-memory compute chiplet devices for inference-time compute acceleration (US 2026, pending) explicitly targets latency-bounded throughput as the optimization metric for transformer model inference. This filing reflects commercial pressure from large language model serving economics, where token generation latency — not peak FLOPS — is the binding constraint. D-Matrix has now filed three related US patents between 2025 and 2026 covering hierarchical DIMC chiplet systems.
SRAM Digital IMC vs. Resistive NVM IMC: Key Architectural Dimensions
Click any row to explore further.
| Dimension | SRAM Digital IMC | Resistive / NVM IMC |
|---|---|---|
| Computation Domain | Digital bitwise logic and arithmetic; no ADC/DAC required | Analog multiply-accumulate (MAC) via continuous conductance states; ADC required |
| Representative Device | 6T or 9T SRAM bitcell (28 nm demonstrated) | RRAM, PCM, STT-MRAM, SOT-MRAM crossbar arrays |
| Peak Energy Efficiency | 437 TOPS/W (Arizona State 28 nm prototype, 2025); 0.68–8.09 TOPS/W (6T SRAM, 2020) | 0.136 pJ/MAC for edge CIM (2022); RRAM-CIM shows area/power advantages over SRAM for same data volume |
| Precision Support | Reconfigurable bit-precision (0.6V–1.1V); FP64 via SOT-MRAM MDCIM (2023) | Primarily low-precision inference; FP64 achieved only with MRAM-based DCIM |
| Primary Application | AI inference DNN layers (convolution, pooling, FC); generative AI; NLP workloads | Binary neural networks, matrix-vector multiplication for CNN inference |
| Scalability Path | Chiplet disaggregation (D-Matrix 2025–2026); scalable mesh-connected IMC arrays (Princeton 2023) | Chiplet benchmarking via SIAM simulator (2021); monolithic 128×64 RRAM + 90 nm CMOS (2020) |
| Process Compatibility | Standard CMOS logic process; mature bitcell design toolchain | Requires backend integration of resistive elements; monolithic CMOS demonstrated at 90 nm |
| Key IP Holders | Arizona State University (US 2025, active); D-Matrix Corporation (US 2025–2026, pending); Princeton University (WO/US 2019–2023) | Literature-dominant; no dominant single patent assignee identified in this dataset |
Frequently Asked Questions: In-Memory Computing Chip Architecture
In-memory computing performs arithmetic or logic operations directly within the memory array itself, either fully in-place (true IMC) or near the array periphery (near-memory computing). Von Neumann architectures require data to shuttle repeatedly between physically separated compute and memory units, creating a performance and energy bottleneck known as the memory wall. Over 80% of the literature sources reviewed cite this bottleneck as the primary motivation for IMC development.
Hangzhou Zhicun (WitMem) Technology Co., Ltd. accounts for 7 of the 8 commercially oriented patent records in this dataset. All were filed in EP and US jurisdictions in June 2025, carrying Chinese priority dates from December 2023. This represents an aggressive international IP prosecution strategy for Chinese-developed CIM technology.
The Arizona State University 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros totaling 3.4 MB, achieving 4.9 TOPS and 437 TOPS/W peak efficiency with a custom ISA featuring SIMD and hardware-loop support (US patent granted active, December 2025). A 6T SRAM implementation at 28 nm achieved 0.68–8.09 TOPS/W with reconfigurable precision from 0.6V to 1.1V supply voltage.
D-Matrix Corporation’s hierarchical DIMC chiplet accelerator system explicitly targets NLP, generative AI, agentic AI, video processing, and cybersecurity workloads. Its 2026 stacked apparatus patent targets latency-bounded throughput as the optimization metric for transformer model inference, reflecting the economics of large language model serving where token generation latency is the binding constraint.
Based on the most recent filings, four distinct directions are identifiable: (1) multi-chip CIM packaging with heterogeneous memory tiers combining DRAM or NAND flash, covered by WitMem’s 2025 EP/US patents; (2) stacked digital IMC chiplets for generative AI inference, covered by D-Matrix’s 2026 US pending filing; (3) flexible topology-aware communication path optimization for IMC cells, from WitMem’s 2026 US filing; and (4) workload-general CIM architectures supporting multiple neural network types simultaneously, from South China University of Technology’s 2024 CN active patent.
US jurisdiction is the primary filing target, designated in 6 of the 8 patent records. EP is the second most common, used by WitMem Technology for its 2025 family. Princeton University also filed across WO, IN, and JP jurisdictions. India appears as a secondary jurisdiction through both Princeton’s IN filing and Applied Intelligence Semiconductors’ domestic IN and WO applications.
Data and insights on this page are based on a limited patent and literature dataset and are for reference only. Figures may not represent the complete technology landscape.