Influence in this dataset is measured by citation count within the searched corpus, and the highest-cited records are older, foundational filings rather than recent RISC-V-specific ones. The most-cited record concerns securing microprocessors against information leakage and physical tampering, followed by filings on asymmetric multicore systems transparent to an operating system and VLIW register-file indexing. These citation counts reflect age as much as importance, since older filings have simply had more time to accumulate citations, so treat them as a signal of historical influence rather than current commercial weight.

No — filings rose from 2 in 2017 to a peak of 15 in 2022, and activity has since flattened rather than continued to climb. Because publication typically lags filing by around 18 months, the most recent year or two in any trend chart will always look lower than it eventually turns out to be, so the true 2025-2026 picture is probably a little stronger than the raw count shows. Even accounting for that lag, though, the growth pattern here is flat rather than accelerating.

The United States receives the largest share of filings in this dataset at 44, well ahead of China at 9 and WIPO/PCT filings at 8. Europe, India and Taiwan each sit in the mid-single digits. That concentration in the US suggests it remains the primary jurisdiction where ISA and processor-design claims are contested, and filers seeking broad protection are more likely to encounter dense prior art there than in secondary jurisdictions.

US20260050569A1, filed by Pragmatic Semiconductor Limited and published February 2026, claims a method for auto-generating processor hardware from a subset of an instruction set using a pre-built library of instruction-hardware representations. It is specific to that library-retrieval and generation mechanism, not to any particular instruction set or to hand-designed subset cores. Anyone building automated core-generation tooling that retrieves hardware representations for a subset of instructions from a master library should review this claim closely; designers implementing a reduced ISA manually are less likely to be affected.

The clearest gaps sit outside the dominant G06F classification: computing based on AI models, digital information transmission and image data processing each appear only once or twice against 83 core filings, meaning very little claim density exists where custom instruction extensions intersect those domains. Co-assignee collaboration is also limited to just 10 pairs across the whole dataset, concentrated around a single inventor cluster, which points to most innovation here happening in isolation rather than through joint filings. A first claim tying a custom instruction extension to a non-CPU hardware unit, such as an AI or image co-processor, would be entering largely unclaimed territory.