Interconnect Metallization Patents: Who Leads, Filing Trends 2026
- Filing has cooled since the 2020 peak. 16 families that year against a flat-to-declining run through 2022 and a near-empty latest year — expected given the ~18-month publication lag, but the slope is real.
- The US carries the filing load. 213 of the tracked records route through the USPTO, versus 29 at the EPO and 20 via WIPO/PCT, so US practice is where prior art density is highest.
- Co-filing is thin and concentrated. Only 10 co-assignee pairs exist across the whole set, and the strongest of them ties an IBM entity to a single partner at 13 shared filings — collaboration here is the exception, not the norm.
What this landscape covers
This dataset tracks 295 patent families at the intersection of back-end-of-line interconnect structures and the materials used to build them: ruthenium liners, low-k and air-gap dielectrics, and copper interconnect formation and fill. The search combines title/abstract language on interconnect metallization with claim-level terms for liner and dielectric materials, scoped to the core CMOS interconnect IPC classes H01L23/532, H01L21/768 and the C23C16 deposition group. It is a claims-first view of a mature back-end-of-line domain, not a survey of front-end transistor materials.
Filings sit almost entirely inside semiconductor device classifications, with secondary activity in coating/surface deposition and printed circuit assemblies. That concentration says the claim space has been worked hard for over a decade — the question for a new filer is which specific material combination or structural variant is still open, not whether the general category is crowded.
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Filing trend and technology composition
Two views of the same 295 families: how filing activity has moved year over year, and which IPC subclasses carry the claim volume.
A 2020 peak followed by a flat-to-declining run
Filings rose from 6 in 2017 to a peak of 16 in 2020, held near that level through the 2022 midpoint at 14, then tapered toward the data cut-off. Treat the last one to two years as undercounted rather than as a genuine drop-off, since publication typically lags filing by around 18 months.
Concentrated in core semiconductor device classes
All 295 records sit under H01L, with H10P and H10W the next-largest secondary groupings. C23C (coating/surface deposition), H10N, H10D, H05K and C25D each carry a smaller slice, marking the deposition, packaging and electroplating angles that interconnect metallization work touches without being centered on.
Shares are the percentage of the 295 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Interconnect Metallization Advanced Materials with Eureka
This page is one run against one query. Ask Eureka your own question about interconnect metallization advanced materials and every answer comes back with the patent numbers behind it.
Try EurekaThe prior art doing the most citation work
Back-end-of-line interconnect structures with varying aspect ratios
A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio.Filed by International Business Machines Corporation, published 2021-08-26.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6368954B1 | Method of copper interconnect formation using atomic layer copper deposition | 314 |
| 2 | US20030127740A1 | Air gaps copper interconnect structure | 216 |
| 3 | US6204192B1 | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over cop… | 170 |
| 4 | US20030003765A1 | Split barrier layer including nitrogen-containing portion and oxygen-containing portion | 144 |
| 5 | US6515368B1 | Semiconductor device with copper-filled via includes a copper-zinc/alloy film for reduced electromigration of… | 137 |
| 6 | US6297155B1 | Method for forming a copper layer over a semiconductor wafer | 133 |
| 7 | US20020042193A1 | Fabrication method of semiconductor integrated circuit device | 102 |
| 8 | US6723631B2 | Fabrication method of semiconductor integrated circuit device | 95 |
| 9 | US6720261B1 | Method and system for eliminating extrusions in semiconductor vias | 91 |
| 10 | US6326301B1 | Method for forming a dual inlaid copper interconnect structure | 86 |
Citation counts inside this corpus skew toward older filings by construction — a 2001-era copper deposition patent has had two decades to accumulate citations that a 2023 filing has not. Read the table as a map of foundational prior art, not a ranking of current relevance.
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Browse MCP servers →What the numbers mean for a filing decision
Three read-throughs from the trend, jurisdiction and citation data that matter more than the raw counts.
The claim space has stopped expanding
A peak in 2020 followed by a flat-to-declining run through 2022 suggests the core material and structural variants for this generation of interconnect metallization have largely been staked out. New filings now need to differentiate on a narrow variant rather than a broad structural claim.
US practice sets the prior art baseline
With 213 of 295 records routed through the USPTO against 29 at the EPO, 20 via WIPO/PCT and 11 in the UK, freedom-to-operate work in this field has to start with US prior art, then check for jurisdiction-specific gaps in Europe or PCT filings.
Co-filing is rare and lopsided
Only 10 co-assignee pairs exist in the entire dataset, and the densest of them links an IBM entity to a single partner at 13 shared filings. Most activity here is single-assignee; joint development deals in this space are the exception.
Foundational deposition patents still anchor the field
The most-cited record dates to early atomic layer copper deposition work and carries 314 citations — evidence that copper fill and liner fundamentals from the early 2000s remain the reference point against which newer material claims get examined.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to interconnect metallization advanced materials, with the prior art for and against each one.
Who holds the claim space
Filing activity concentrates among a handful of large semiconductor manufacturers and equipment makers, with recent-year momentum flat across the tracked assignees.
Leaders have paused, not exited
Every one of the assignees tracked for recent momentum — including TSMC, IBM, Intel and Lam Research — shows zero filings in the latest year. Given the publication lag, this reads as a reporting gap rather than a retreat from the technology.
Lam Research anchors two of the strongest pairings
Lam Research appears in two of the top co-assignee relationships, each at 7 shared filings, pointing to process-equipment-to-device collaboration on deposition and etch steps rather than pure materials science partnerships.
A long tail behind a small set of IDMs
Large integrated device manufacturers and one dominant foundry account for the bulk of sustained filing, with the remainder spread thinly across smaller semiconductor and materials suppliers — a structure typical of back-end-of-line process IP.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Company (TSMC) | 0 | — |
| International Business Machines Corporation (IBM) | 0 | — |
| Intel Corporation | 0 | — |
| Lam Research Corporation | 0 | — |
| Infineon Technologies North America Corp. | 0 | — |
| NEC Electronics Corporation | 0 | — |
| Advanced Micro Devices, Inc. (AMD) | 0 | — |
| Micron Technology, Inc. | 0 | — |
Where to take this analysis
The trend and assignee data point to specific next steps depending on whether you're scoping freedom-to-operate or looking for a filing angle.
Check the white space chips against your own claim draft
The under-claimed sub-areas above — ruthenium liner adhesion, air-gap sequencing, split barrier layering — are candidates for a first claim, but each needs a targeted search before you commit.
Explore in Eureka →Map the US filing density before drafting
With 213 of 295 records routed through the USPTO, any new US filing needs a tight comparison against that concentration before claims are finalised.
Run a citation map in Eureka →Watch for the lagged latest-year data to fill in
Zero recent-year momentum across every tracked assignee is consistent with the ~18-month publication lag, not a real stop in activity — revisit this view in a future data cut to confirm.
Set a monitoring alert in Eureka →Common questions about this landscape
It covers the materials and structures used to build back-end-of-line electrical connections in a semiconductor device, including copper interconnect formation, ruthenium liner materials, and low-k or air-gap dielectric layers that separate the conductive lines. The dataset is scoped by IPC classes H01L23/532, H01L21/768 and C23C16, which together capture interconnect structure, dielectric isolation and coating/deposition claims. It excludes front-end transistor materials and most packaging-level interconnect work outside those classes.
Filings rose from 6 in 2017 to a peak of 16 in 2020, then held roughly flat through 2022 before tapering toward the most recent tracked year. Part of that apparent decline is a publication-lag artefact: patents typically publish around 18 months after filing, so the last one to two years in any dataset are undercounted rather than genuinely quiet. The flat run from 2020 to 2022 is a more reliable signal that the core structural and material claim space had matured by that point.
Filing activity concentrates among a small group of large integrated device manufacturers, a dominant foundry, and semiconductor process equipment makers, with a long tail of smaller suppliers behind them. Recent-year momentum figures show zero filings in the latest tracked year across all of the leading assignees checked, which is consistent with publication lag rather than an actual halt. The full ranked assignee table, rendered separately from this prose, gives the exact order and family counts.
Relative to the dense core claim space around copper fill and low-k dielectrics, several adjacent branches show thinner coverage: ruthenium liner adhesion layers, air-gap dielectric formation sequencing, split barrier layers combining nitrogen- and oxygen-containing portions, and electroplating-based via fill under the C25D classification. These are not guaranteed-open — they are directions that warrant a targeted freedom-to-operate search before drafting a claim, given how much of the surrounding space is already occupied.
Heavily concentrated in the United States: 213 of the 295 tracked records have a US receiving office, versus 29 at the European Patent Office, 20 filed via the WIPO/PCT route, and smaller counts in the UK, Austria and Australia. That skew means US prior art sets the practical baseline for novelty and freedom-to-operate assessments in this field, with European and PCT filings worth checking separately for jurisdiction-specific gaps rather than assumed overlap with the US corpus.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.