Logic & Memory Devices Patents: Who Leads, Where the Gaps Are 2026
- 36.9% concentration. The top five assignees alone account for 135,283 of the 366,872 records in scope — filing here means crossing occupied claim space, not empty ground.
- Filings cooling from a 2020 peak. Volume ran 699 in 2017, peaked at 1,061 in 2020, then declined 32% from 1,003 in 2021 to 686 in 2024 — the last year the trend can be read as complete.
- G11C dwarfs every other class. Static and digital memories (G11C) carries 4.6% of all 366,872 records, more than three times the share of the next most common subclass, H01L.
Filing growth compares 2021 (1,003 records) with 2024 (686) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 366,872 records in scope (CR5), not by the ranked leaders only.
What the logic and memory device filing record actually shows
The dataset covers 366,872 published records filed against logic and memory device terms — transistor gates, memory cells, signal paths, circuit timing, device fabrication and process control — between 2015 and the 2026-08-31 cut-off. It is a mature, densely claimed field: five companies hold more than a third of all records, and a single IPC subclass, G11C, appears on close to one in twenty filings. That density is a filing-strategy signal, not a technology-maturity one — occupied claim space still leaves room for narrower, better-drafted claims underneath it.
Most receiving-office activity sits with the United States, with much smaller but present volume through the EPO, WIPO's PCT route, Singapore, the UK and Australia — consistent with a field where core memory-cell and logic-device IP is filed first in the US and extended selectively abroad.
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Filing trend and technology composition
Two views of the same 366,872-record dataset: filings by year, and the IPC subclasses those filings carry.
Filing trend, 2017–2026
Volume rose from 699 in 2017 to a peak of 1,061 in 2020, then fell 32% from 1,003 in 2021 to 686 in 2024 — the most recent year that can be treated as complete, since publication lags filing by roughly 18 months and 2025-2026 figures will still fill in.
IPC subclass composition
G11C (static and digital memories) leads at 4.6% of all records, ahead of H01L (1.4%), H10B memory device manufacture (1.3%), H10D general semiconductor devices (0.6%) and G06F data processing (0.6%). Records can carry more than one class, so these shares do not sum to 100%.
Shares are the percentage of the 366,872 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Logic & Memory Devices Patent Landscape with Eureka
This page is one run against one query. Ask Eureka your own question about logic & memory devices patent landscape and every answer comes back with the patent numbers behind it.
Try EurekaThe most-cited records in the field
US5436506A — Semiconductor memory device and the manufacturing method thereof
An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of a third oppositely adjacent memory cell. Each pair of coupled gates is formed separate from the access transistor gates in adjacent memory cells, with word lines connecting the separated access transistor gates above an insulating layer.Filed by Samsung Electronics, 1995-07-25 — a foundational SRAM cell-layout patent still cited across later memory device filings.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US6046935A | Semiconductor device and memory system | 2,772 |
| 2 | US5774397A | Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermi… | 1,943 |
| 3 | US5903495A | Semiconductor device and memory system | 1,096 |
| 4 | US20050023656A1 | Vertical system integration | 785 |
| 5 | US6643188B2 | Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell | 721 |
| 6 | US6657891B1 | Semiconductor memory device for storing multivalued data | 688 |
| 7 | US6501111B1 | Three-dimensional (3D) programmable device | 624 |
| 8 | US20100246266A1 | Nonvolatile memory device and related programming method | 528 |
| 9 | US6151244A | Dynamic semiconductor memory device | 468 |
| 10 | US6301164B1 | Antifuse method to repair columns in a prefetched output memory architecture | 463 |
Citation counts inside a searched corpus favour older filings — read this as a map of influential prior art, not of current filing activity.
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Browse MCP servers →What the filing data signals for strategy
Three patterns in the record volume, class distribution and citation graph that matter more than any single ranking.
A narrow group holds a third of the field
The top five assignees combine for 135,283 records, 36.9% of everything in scope; the top ten reach 47.5%. Below that sits a long tail — filing here means either licensing around the leaders' cell and array architecture claims or working in the narrower branches they have not claimed as densely.
Growth has cooled from its 2020 peak, not collapsed
Filing volume peaked at 1,061 in 2020 and has since declined, down 32% from 1,003 filings in 2021 to 686 in 2024 — the last complete year. That is a cooling of pace among established players, not evidence the field is closing; the 2025-2026 figures are still incomplete due to publication lag.
Memory-cell architecture claims dominate the class mix
G11C static and digital memory claims appear on 4.6% of all 366,872 records, more than three times the share of H01L semiconductor devices (1.4%) or H10B memory device manufacture (1.3%). Fabrication-process classes such as H10W and H10P sit well under 1% each — comparatively open ground.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to logic & memory devices patent landscape, with the prior art for and against each one.
Assignee landscape: leaders, momentum and gaps
The ranking covers 100 companies counted by patent family; it is the full set the data endpoint returns, not a curated top list. A handful of names carry disproportionate volume, and recent-year filings from every one of them are down sharply year-on-year — consistent with the field's post-2020 cooling.
One assignee sets the scale for the field
The leading assignee holds 44,464 records, well ahead of fifth place at 12,766 and tenth place at 5,495 — a steep drop-off that marks this as a field with a dominant filer rather than several evenly matched ones.
Every tracked leader is filing far less than a year ago
Recent-year filings from the largest assignees are down steeply — Samsung Electronics -91%, Micron -88%, TSMC -88%, Kioxia -96%, Yangtze Memory -90%, SK hynix -97%. Read this against the 18-month publication lag: it reflects an incomplete latest year more than a real filing halt.
Filing partnerships cluster inside single corporate groups
The ten identified co-assignee pairs are almost entirely parent-subsidiary pairings — Fujitsu with Fujitsu VLSI, Toshiba with its microelectronics unit, Mitsubishi Electric with its engineering arm — rather than cross-company joint filings, suggesting collaboration here is organisational, not competitive alliance.
| Assignee | Recent year | YoY |
|---|---|---|
| Samsung Electronics Co., Ltd. | 14 | -91% |
| Micron Technology, Inc. | 6 | -88% |
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 4 | -88% |
| Kioxia Corporation | 3 | -96% |
| Yangtze Memory Technologies Co., Ltd. | 2 | -90% |
| SK hynix Inc. | 1 | -97% |
| Toshiba Corporation | 0 | -100% |
| Fujitsu Limited | 0 | — |
Where to take this analysis
The dataset points to specific follow-up work depending on whether the goal is freedom-to-operate, licensing, or new claim drafting.
Map freedom-to-operate against the top holders
With 36.9% of records held by five assignees, any new filing in core memory-cell or logic-device architecture should be checked against their family claims before drafting begins.
Explore assignee claims in EurekaProbe the under-claimed IPC branches
H10W and H10P sit at a fraction of G11C's density. That gap is worth testing with a freedom-to-operate and prior-art search before assuming it is truly open.
Run a white-space search in EurekaTrack the post-2020 filing shift
The move from 1,061 filings in 2020 to 686 in 2024 changes who is actively defending claim space. Monitoring which assignees keep filing versus pull back reshapes negotiating leverage.
Set up filing alerts in EurekaCommon questions about the logic and memory device patent landscape
One assignee leads with 44,464 records, a scale well beyond fifth place at 12,766 and tenth at 5,495 records in the ranking. The top five assignees combine for 135,283 records, 36.9% of the 366,872 records in scope, and the top ten reach 47.5%. That leaves a long tail of smaller filers below a clearly dominant handful, so competitive analysis in this field should focus first on the leader's family claims rather than assume an evenly spread market.
Filings peaked at 1,061 in 2020 and have since fallen 32%, from 1,003 in 2021 to 686 in 2024, the last year that can be treated as complete. Because publication lags filing by roughly 18 months, the 2025 and 2026 figures are still filling in and should not be read as evidence of a further drop. The honest read is a cooling from a 2020 high, not a collapse in activity.
G11C, covering static and digital memories, is the clear leader at 4.6% of all 366,872 records, more than three times the share of the next largest class, H01L semiconductor devices at 1.4%. H10B memory device manufacture (1.3%), H10D general semiconductor devices (0.6%) and G06F data processing (0.6%) follow well behind. Smaller classes such as H10W and H10P sit under 1%, marking them as comparatively under-claimed relative to the core memory-cell classes.
US5436506A is a Samsung Electronics SRAM memory cell patent filed in 1995 that claims an access transistor gate structure formed from a layer separate from the word line, with paired gates linked across adjacent memory cells. It remains a reference point in the field's citation graph because later memory device patents build on or route around this specific gate-and-word-line layering approach. Anyone drafting new SRAM cell-layout claims should check this record's specific layer-separation limitation before assuming their design is clear of it.
The class data points to fabrication and process-integration branches — H10W and H10P — which carry a fraction of the record volume that G11C or H10B do, despite sitting adjacent to heavily claimed memory-cell and manufacture classes. Circuit-timing calibration and process-control feedback claims outside the core G11C cell-architecture space also show comparatively light density. None of this guarantees the space is unclaimed by non-patent prior art, but the IPC distribution is the first signal worth testing with a targeted freedom-to-operate search.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.