Low-Temp 3D Integration Patents: Who Leads, Where the Gaps Are 2026
- Top 5 filers hold 49.1% of the field. 52 of the 106 records in scope sit with just five assignees, while a long tail of single- and low-filing entrants fills out the rest of the 37-company ranking.
- H01L dominates, but H10P is the second-largest bucket. 84.9% of records carry an H01L classification, and 26.4% also carry H10P — sequential-integration-adjacent claims are already spreading beyond core device structure filings.
- The most-cited record in the set is a CVD precursor preheating patent, not a sequential-integration one. Its 425 citations show the field's influence still runs through thermal-budget process control from earlier device generations, not the newer upper-tier-device claims.
Top-5 share is the combined record count of the five largest assignees divided by all 106 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Low-temperature processing for 3D integration sits at the intersection of thermal budget control and sequential device stacking: the challenge of building an upper-tier device on top of a finished lower tier without damaging interconnects, diffusing dopants where they shouldn’t go, or breaking process compatibility with materials already on the wafer. This dataset covers 106 published records filed between 2015 and mid-2026, drawn from search terms spanning low temperature process integration, thermal budget, and integration-specific concepts like activation at reduced temperature and sequential integration.
Publication lags filing by roughly 18 months, so the 2025-2026 activity shown here understates true filing volume for those years; treat the most recent year as a floor, not a ceiling.
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Filing trends and technology composition
Filing counts and IPC composition for the 106 records in scope, drawn directly from the underlying dataset with no adjustment for publication lag.
Filing trend, 2017-2026
Filings rose from 2 in 2017 to a peak of 4 in 2025; 2026 is a partial year and the true count for the last two years is likely higher once late publications land. With fewer than four complete years since the lag window closes, no growth rate can be stated reliably.
IPC subclass composition
H01L (semiconductor devices generally) covers 84.9% of records and anchors the field. H10P and H10B, at 26.4% and 19.8%, mark the memory-device and stacking-specific claims; C23C, C30B, H10W and G02B each cover a smaller slice, pointing to deposition, crystal growth and optical-integration work that sits adjacent to the core.
Shares are the percentage of the 106 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on Low-Temperature Processing for 3D Integration with Eureka
This page is one run against one query. Ask Eureka your own question about low-temperature processing for 3d integration and every answer comes back with the patent numbers behind it.
Try EurekaRepresentative and most-cited records
US6140679A — Zero thermal budget manufacturing process for MOS-technology power devices
A zero thermal budget manufacturing process for a MOS-technology power device. The method forms a conductive insulated gate layer on a lightly doped semiconductor surface, removes it from selected portions, and implants a first dopant through the gate layer acting as a mask, with dose and energy chosen to produce heavily doped regions substantially aligned to the mask edges.Filed by SGS-THOMSON MICROELECTRONICS S.R.L., granted 2000-10-31 — one of the earlier zero/low-thermal-budget process filings in this corpus.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20020188376A1 | Preheating of chemical vapor deposition precursors | 425 |
| 2 | US6316806B1 | Trench transistor with a self-aligned source | 106 |
| 3 | US20020038886A1 | Method of forming trench transistor with self-aligned source | 81 |
| 4 | US6451692B1 | Preheating of chemical vapor deposition precursors | 75 |
| 5 | US6583010B2 | Trench transistor with self-aligned source | 50 |
| 6 | US5192708A | Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization | 45 |
| 7 | US6362063B1 | Formation of low thermal budget shallow abrupt junctions for semiconductor devices | 44 |
| 8 | US20020025643A1 | Method for using thin spacers and oxidation in gate oxides | 41 |
| 9 | US6566210B2 | Method of improving gate activation by employing atomic oxygen enhanced oxidation | 37 |
| 10 | US6329704B1 | Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer | 35 |
Citation counts inside this searched corpus favour older filings and should be read as a signal of influence on the field, not of current commercial relevance.
Each row carries its publication number; clicking a row searches Eureka by that number.
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Browse MCP servers →What the numbers mean for a filing decision
Three patterns worth acting on before drafting new claims or scoping freedom-to-operate in this space.
The top of the field is settled, the rest is open
With the leader at 17 records and fifth place at just 6, the gap between the top assignee and the rest of the top 5 is wide. Below tenth place (3 records), filing activity thins into a long tail — most of the 37 ranked companies hold only one or two records.
Sequential-integration claims are not confined to one class
84.9% of records sit in H01L, the general semiconductor-device bucket, but over a quarter also carry H10P classification. Because a record can carry multiple IPC codes, this overlap signals that upper-tier device claims are being drafted across class boundaries rather than into one tidy bucket.
Influence still traces back to CVD precursor work
The most-cited record in the corpus concerns preheating chemical vapor deposition precursors, not sequential integration directly. Older thermal-process-control patents continue to anchor citation trees even as newer filings address stacking-specific problems.
Filing activity is US-centred with a PCT and EPO tail
United States receiving-office filings account for 65 of the 106 records, with WIPO (PCT) at 14 and EPO at 10. China, Australia and the UK together account for a small remainder, suggesting most applicants are still routing global protection through a US-first strategy.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to low-temperature processing for 3d integration, with the prior art for and against each one.
Who holds the core claims, and where the gaps are
The ranked leaders sit alongside a long tail of single- and low-filing entrants; momentum data for the latest year shows even top-ranked assignees with no recorded filings yet, consistent with publication lag rather than a slowdown.
A single assignee holds the largest share
The top-ranked assignee's 17 records is more than double the fifth-place count of 6, giving it outsized influence over how upper-tier device and interconnect-reliability claims get drafted in this space.
A compressed middle tier
Between fifth place (6 records) and tenth place (3 records), six assignees compete closely for the same claim space, which is where freedom-to-operate risk is most concentrated for a new entrant.
Co-filing is rare and concentrated
Only 5 co-assignee pairs appear in the corpus, with the strongest pair filing together 4 times. Co-assignment is the exception here, not a common route to shared claims.
| Assignee | Recent year | YoY |
|---|---|---|
| International Business Machines Corporation (IBM) | 0 | — |
| Micron Technology, Inc. | 0 | — |
| Council of Scientific & Industrial Research | 0 | — |
| Atmel Corporation | 0 | — |
| Applied Materials, Inc. | 0 | — |
| Advanced Micro Devices, Inc. (AMD) | 0 | — |
| Infineon Technologies Americas Corp. | 0 | — |
| GlobalFoundries Inc. | 0 | — |
Where to take this research
The dataset points to a settled top tier and an open middle and long tail. The next steps depend on whether you're scoping freedom-to-operate or looking for a filing gap.
Run a freedom-to-operate check against the mid-tier cluster
The six assignees ranked 5-10 hold closely spaced counts and are the most likely source of near-term claim conflicts for new entrants drafting upper-tier device or interconnect-reliability claims.
Explore assignee claims in EurekaDraft into the under-claimed branches before they fill in
G02B, C30B and C23C overlaps with the H01L core are all lighter than the H10B and H10P buckets, suggesting room for a first claim that bridges optical, crystal-growth or deposition process steps with low-temperature integration.
Check white space in EurekaVerify citation-driven assumptions against filing date
The most-cited record in this corpus is an older CVD precursor patent, not a recent sequential-integration filing. Confirm any freedom-to-operate conclusion drawn from citation rank against the actual publication date before relying on it.
Pull full citation trees in EurekaFrequently asked questions
The ranking covers 37 companies, with the top assignee holding 17 of the 106 records in scope and the top 5 combined holding 49.1% of all records. Below the top 10 (which together hold 68.9%), filing counts drop quickly into a long tail of companies with only one or two records each. This means the field has a small settled core of repeat filers and a much larger group of occasional entrants, which is typical for a specialised process technology rather than a broad platform technology.
Thermal budget refers to the total heat exposure — combined temperature and time — a wafer can tolerate during a process step before it damages previously formed structures, dopant profiles, or interconnects. In sequential 3D integration, staying within a low thermal budget while forming an upper-tier device on top of a finished lower tier is the central engineering problem this dataset's claims address. Patent claims in this space typically specify a maximum process temperature or an activation method designed to work at reduced temperature, which is why 'activation at reduced' and 'thermal budget' both appear as search terms defining this landscape.
Patent applications are typically published around 18 months after filing, so any record filed in late 2025 or 2026 may not yet be publicly visible in this dataset as of the 2026-07-31 cut-off. The filing trend shows 2026 at 0 and 2025 as the peak year at 4, but both figures should be read as a floor rather than a final count. Anyone using this trend to judge whether activity is slowing should wait for at least one more publication cycle before drawing that conclusion.
H01L covers 84.9% of the 106 records in scope and should be the starting point for any search, but 26.4% of records also carry H10P classification and 19.8% carry H10B, so a search limited to H01L alone will miss a meaningful share of relevant filings. Smaller but still notable overlaps appear in C23C (10.4%), H10D (8.5%), C30B (6.6%), H10W (6.6%) and G02B (5.7%). Because records can carry multiple IPC codes, a thorough search should pull all of these classes rather than relying on a single primary classification.
The IPC composition suggests lighter classification density in branches like G02B (optical-integration compatibility), C30B (crystal-growth-based dopant activation) and C23C (coating and surface deposition for interconnect reliability), relative to the dominant H01L and H10P/H10B buckets. Lighter classification density means fewer competing claims, not that a technology is unworkable or unwanted. Anyone considering a filing in these adjacent branches should still run a full search against the top assignees' full portfolios, since a company's core claims in H01L may extend implicitly into these lighter-filed areas.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.