In this dataset it refers to hardware and protocol architectures that let processors, accelerators and memory expansion devices share memory coherently across a fabric, rather than through traditional load/store-only buses. Claims typically cover coherency protocols, address translation, page migration and memory pooling or expansion devices. The search scope combines cache-coherent interconnect and memory-pooling terms with access-latency, coherency-protocol and disaggregation terms, which is why the corpus skews heavily toward G06F digital-data-processing claims (81.9% of the 3,238 records in scope).

Filing is highly concentrated: the top five assignees together account for 75.1% of all 3,238 records in scope, and the top ten reach 84.3%. A single leading assignee alone accounts for 1,811 records, with the count falling off sharply after fifth place (84 records) and tenth place (34 records). That pattern — one dominant holder plus a long tail of much smaller filers — is a stronger signal than any single company name, since the ranked list itself only covers 100 companies rather than the whole field.

Growth has flattened rather than continuing its earlier climb. Filings rose from 116 in 2017 to a peak of 495 in 2022, then moved only from 370 in 2021 to 373 in 2024, a +1% change over that span. Numbers for 2025 and 2026 appear lower still, but that reflects the roughly 18-month lag between filing and publication rather than an actual drop in activity, so those most recent years should not be read as a decline.

The thinnest coverage sits in physical-layer and wireless-adjacent classes: H03K (pulse technique and logic circuits) and H01L (semiconductor devices) each account for only 1.4% of the 3,238 records in scope, and H04W (wireless communication networks) for 1.9%. These low shares, next to a G06F core at 81.9%, suggest that link-reliability mechanisms and non-traditional physical layers for coherent memory fabrics carry far less claim density than the core coherency and pooling protocols, making them a more open area to file narrow, defensible claims.

This 2026 filing from Unifabrix claims a way to carry CXL memory semantics over physical layers based on IEEE 802.3 PMA, using a Resource Provisioning Unit to translate between CXL requests and that encapsulated traffic. It is a fairly specific combination — anyone building CXL-over-Ethernet-class-PHY disaggregation with an equivalent translation function should read its claims closely. It does not reach implementations that stay on native CXL, PCIe or proprietary interconnect layers, which remain governed by older, more heavily cited art already in the corpus.