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The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →Filing growth compares 2021 (143 records) with 2024 (97) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,300 records in scope (CR5), not by the ranked leaders only.
This dataset tracks patent families filed against memory subsystem architecture and bandwidth optimization — specifically DRAM scheduling, latency hiding, channel interleaving, refresh management and high bandwidth memory — restricted to IPC classes covering digital data processing, static and digital memories, and input/output data transfer. It spans filings from 2015 through the mid-2026 data cut-off, giving a decade-plus view of how memory controller and subsystem claims have been staked out.
The corpus is dominated by digital data processing and static/digital memory classifications, with smaller but consistent overlap into semiconductor devices, AI-model computing and display control — evidence that memory bandwidth claims increasingly touch adjacent domains rather than staying siloed in classic controller design.
Pick a task. Every answer cites the patents behind it.
Two views of the same 1,300-family corpus: how filing volume has moved year over year, and which IPC subclasses carry the claim density.
Filings ran at 91 in 2017, climbed to a peak of 168 in 2022, and have fallen back to single digits by the most recent partial year. Because publication lags filing by roughly 18 months, the last one to two years will always look thinner than they eventually turn out to be — but the decline from the 2022 peak predates that lag and points to a genuine slowdown in new memory-subsystem filing activity, not just a reporting artifact.
G06F (electric digital data processing) and G11C (static and digital memories) together account for the large majority of records, with G06T, H01L, H04L, G06N, G09G and H03M each contributing a modest secondary share — signalling that most contested claim territory sits squarely in controller logic and memory cell architecture, with imaging, semiconductor fabrication and AI-adjacent filings as satellite activity.
Shares are the percentage of the 1,300 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
This page is one run against one query. Ask Eureka your own question about memory subsystem and bandwidth optimization and every answer comes back with the patent numbers behind it.
Try EurekaA memory system includes a memory device, a control circuit, and a memory controller. The memory device includes a plurality of memory regions, a candidate register set storing a plurality of candidate parameter sets corresponding to temperature ranges, respectively, a mode register set storing a temperature range and a refresh management parameter set. The control circuit stores, based on the temperature range, a first candidate parameter set of the plurality of candidate parameter sets as the refresh management parameter set in the mode register set. The memory controller obtains the refresh management parameter set from the memory device, based on an updated temperature range, counts actiAbstract text truncated as published.


| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20150325272A1 | In-memory lightweight coherency | 462 |
| 2 | US6510503B2 | High bandwidth memory interface | 446 |
| 3 | US20150324290A1 | Hybrid memory cube system interconnect directory-based cache coherence methodology | 436 |
| 4 | US6877076B1 | Memory controller with programmable configuration | 295 |
| 5 | US6104417A | Unified memory computer architecture with dynamic graphics memory allocation | 269 |
| 6 | US20010047450A1 | High bandwidth memory interface | 211 |
| 7 | US20080028137A1 | Method and Apparatus For Refresh Management of Memory Modules | 199 |
| 8 | US6625685B1 | Memory controller with programmable configuration | 193 |
| 9 | US20080028136A1 | Method and apparatus for refresh management of memory modules | 176 |
| 10 | US20080109597A1 | Method and apparatus for refresh management of memory modules | 162 |
Citation counts favour older filings simply because they have had longer to accumulate citations inside this searched corpus — read them as a measure of influence on subsequent filers, not as a signal of which patents matter most today.
Each row carries its publication number; clicking a row searches Eureka by that number.
When you want the answer in the next five minutes.
The agent works the prompt against patents and technical literature, citing every source.
Run your analysis now →When it has to run inside your own pipeline.
Patent search, landscape analysis and assignee resolution as MCP tools. Drop them into any agent framework, or call REST directly.
Browse MCP servers →Three patterns stand out once volume, geography and citation depth are read together.
Filing volume roughly doubled between 2017 and its 2022 peak, then fell sharply enough that the decline outruns what publication lag alone would explain. Combined with negative year-on-year momentum across every tracked assignee, this reads as a maturing claim space rather than a temporary dip.
The United States receives more filings than Europe, WIPO, India, China and Taiwan combined. Litigation and licensing exposure for memory subsystem claims is concentrated there; freedom-to-operate work that only checks EPO or CNIPA coverage will miss most of the contested territory.
The most-cited records concern in-memory coherency, high bandwidth memory interfaces and hybrid memory cube interconnects — architectural building blocks that later refresh-management and scheduling filings build directly on top of.
Co-assignee activity is thin relative to total volume, and the strongest pairings link a manufacturer to a university research foundation rather than to another manufacturer — suggesting most competitive advantage here is built through solo filing, not joint development.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to memory subsystem and bandwidth optimization, with the prior art for and against each one.
Assignee activity across this corpus is not a story of a rising challenger — it is a story of an entire field slowing down together.
Two filings in the latest year against a 33% year-on-year decline — the smallest drop among major assignees tracked, which in this dataset counts as relative resilience rather than strength.
Samsung remains active with two filings in the latest year, including the representative refresh-management filing in this dataset, but that volume sits 93% below its prior-year pace.
AMD, Micron and SK hynix each show zero filings in the latest tracked year, a full stop rather than a slowdown. Whether that reflects a strategic pause, a shift to trade secrecy, or simply publication lag will only become clear once later filing years fully populate.
| Assignee | Recent year | YoY |
|---|---|---|
| Intel Corporation | 2 | -33% |
| Samsung Electronics Co., Ltd. | 2 | -93% |
| Advanced Micro Devices, Inc. (AMD) | 0 | -100% |
| Micron Technology, Inc. | 0 | -100% |
| SK hynix Inc. | 0 | -100% |
| Google LLC | 0 | — |
| Qualcomm Incorporated | 0 | -100% |
| International Business Machines Corporation (IBM) | 0 | — |
The trend and assignee data point to a field past its filing peak but still anchored by a handful of foundational patents. Two directions make sense from here.
Momentum data matters more than cumulative share in a declining field — an assignee filing steadily at low volume may be staking out the remaining open ground while larger holders pull back.
Explore assignee momentum in EurekaNew scheduling and refresh-management claims tend to sit downstream of the coherency and interface patents with the deepest citation counts in this corpus; checking against those first narrows the search fast.
Run a freedom-to-operate check in EurekaFiling volume in this corpus peaked at 168 in 2022 and has fallen sharply since, down to single digits in the latest partial year. Part of that drop is a reporting artifact: publication typically lags filing by around 18 months, so the most recent one to two years will always look artificially thin. But the decline starting well before the cut-off, combined with negative year-on-year momentum at nearly every major assignee tracked, suggests a genuine slowdown in new filing activity rather than just an undercount.
The assignee ranking in this dataset is derived from 1,300 patent families, with large DRAM and processor manufacturers holding meaningful positions alongside academic research foundations that co-file with them. Rather than a single dominant leader, the field shows concentration among a small group of established semiconductor and computing firms, each now filing at a reduced pace compared to prior years. Checking the full ranking table alongside the momentum figures gives a more accurate read than headline volume alone, since some large holders have gone quiet in the most recent tracked year.
The United States is by far the primary filing destination in this corpus, with 792 of 1,300 records receiving at USPTO — more than Europe, WIPO, India, China and Taiwan combined. That concentration means litigation and licensing risk for memory controller and bandwidth-optimization claims is heavily weighted toward US jurisdiction. Freedom-to-operate reviews that focus only on European or Chinese filings will miss the bulk of the contested claim territory.
The core of this corpus sits in electric digital data processing (G06F) and static/digital memories (G11C), which together account for the large majority of records. Secondary overlap appears in image data processing, semiconductor devices, digital transmission, AI-model computing, display control and coding/code conversion — each a modest but consistent share. This pattern indicates that bandwidth and refresh-management claims increasingly reach into adjacent domains like AI workload scheduling and display pipelines rather than staying confined to classic memory controller design.
US20260141940A1, assigned to Samsung Electronics and published 2026-05-21, describes a memory system with a memory device holding a candidate register set of parameter sets tied to temperature ranges, and a memory controller that selects and updates a refresh management parameter set based on measured temperature. In practice this claims temperature-adaptive refresh parameter selection as a mechanism, not refresh management generally. Anyone designing refresh logic that varies parameters by temperature range should review this filing's specific claim language before assuming a workaround is clear, since the mechanism it protects is fairly narrow but sits in an active filing area.
Go past this page: query the whole memory subsystem and bandwidth optimization corpus yourself, in your own scope.
Every answer comes back with patent numbers you can open.
Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company's registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.