Wafer-Level MEMS Vacuum Packaging Patents: Top Companies & Trends 2026
- 31.6% concentration at the top. The five leading assignees hold 325 of 1,027 records in scope — a dense core with a long tail behind it.
- Filing has cooled from its 2019 peak. Filings ran 51 in 2019 and fell -48% from 2021 (31) to 2024 (16), the last year with reasonably complete data.
- H01L and B81C dominate the claim space. 51.8% of records carry a H01L semiconductor-device class and 33.0% carry B81C MEMS-manufacturing — the two densest zones to search before filing.
Filing growth compares 2021 (31 records) with 2024 (16) — a three-year span. 2024 is the most recent year we treat as complete: publication lags filing by roughly 18 months, so 2025 onwards are still filling in and any growth rate that ends there would understate the field. Top-5 share is the combined record count of the five largest assignees divided by all 1,027 records in scope (CR5), not by the ranked leaders only.
What this landscape covers
Wafer-level vacuum packaging sits at the intersection of semiconductor process integration and MEMS device design: sealing a cavity around a micromachined structure at the wafer stage, before singulation, to hold a controlled pressure over the device’s working life. The 1,027 records in scope span RF filters, inertial sensors, pressure sensors and other micromachined devices wherever the packaging claim itself — the cavity, the seal, the bonding method, the getter — is the inventive core, not just the device sitting inside it.
Filings cluster around a handful of large semiconductor and RF-component holders alongside a long tail of single- or few-filing entrants, a pattern typical of a packaging technology that underpins several downstream product lines rather than one narrow application.
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Filing trend and technology composition
Two views of the same 1,027 records: how filing activity has moved year over year, and how the technology splits across IPC subclasses. Because a single record can carry several IPC codes, the class shares below add up to more than 100% of the record total.
Filings rose to a 2019 peak, then eased
Annual filings ran from 38 in 2017 to a peak of 51 in 2019. The 2021-to-2024 window shows a -48% move (31 to 16); treat 2025 and 2026 as still filling in, since publication typically lags filing by around 18 months.
H01L and the two MEMS-specific B81 classes carry the field
H01L (51.8%) and B81C (33.0%) are the two largest classes, with B81B (31.8%) close behind — together these three account for the bulk of the packaging and micromachining claim space, while H10W, H10P and H03H mark out the RF-filter and impedance-network side of the dataset.
Shares are the percentage of the 1,027 records in scope. A patent can carry several IPC classes, so the shares add up to more than 100%.
Go deeper on MEMS & NEMS — Wafer-Level MEMS Vacuum Packaging Patent Landscape with Eureka
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Try EurekaThe most-cited records in this space
Wafer level MEMS packaging (US6953985B2)
An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements sealed to a MEMS device die array to produce a sealed MEMS device package array. Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.Filed by North Star Innovations; illustrates the lidded-array approach to pre-singulation sealing that recurs across the most-cited records in this set.
| # | Publication no. | Patent title | Citations |
|---|---|---|---|
| 1 | US20070190747A1 | Wafer level packaging to lidded chips | 540 |
| 2 | US20040016995A1 | MEMS control chip integration | 330 |
| 3 | US20190068164A1 | 5G BAND n79 ACOUSTIC WAVE RESONATOR RF FILTER CIRCUIT | 284 |
| 4 | US7109635B1 | Wafer level packaging of materials with different coefficients of thermal expansion | 249 |
| 5 | US20120326248A1 | Methods for CMOS-MEMS integrated devices with multiple sealed cavities maintained at various pressures | 247 |
| 6 | US7635636B2 | Wafer level packaging of materials with different coefficients of thermal expansion | 244 |
| 7 | US6479320B1 | Vacuum package fabrication of microelectromechanical system devices with integrated circuit components | 243 |
| 8 | US20120098074A1 | MEMS device with release aperture | 223 |
| 9 | US20020000646A1 | Vacuum package fabrication of integrated circuit components | 205 |
| 10 | US20160347609A1 | MEMS Packages and Methods of Manufacture Thereof | 185 |
Citation counts inside a searched corpus favour older filings; read them as a signal of influence on later filers, not as a measure of current commercial relevance.
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Browse MCP servers →What the numbers mean for a filing decision
Three readings of the dataset that matter more for strategy than the raw counts alone.
The core is occupied, not empty
With 325 of 1,027 records held by five assignees, the central packaging claims — cavity sealing, lid bonding, getter placement — are heavily prior-arted. New filings in this exact space compete against dense, well-cited prior art rather than open ground.
Activity has cooled from its peak
The 2019 peak of 51 filings has not been repeated; the 2021-to-2024 window shows a -48% decline. That is consistent with a technology whose core claims are already staked out, pushing new work toward adjacent or combination claims.
Semiconductor integration outweighs pure MEMS process claims
More records sit in the general semiconductor-device class (H01L) than in the MEMS-specific manufacturing class (B81C), suggesting much of the recent claim activity is about integrating vacuum-sealed MEMS with surrounding IC process flow rather than the sealing process in isolation.
Eureka can read the same corpus for gaps instead of for coverage: under-claimed branches adjacent to mems & nems — wafer-level mems vacuum packaging patent landscape, with the prior art for and against each one.
Who holds the ground, and who is still moving
The ranked list covers 100 assignees by record count; it is the full ranking the dataset returns, not a curated top tier. Recent-year activity for several of the leading names has dropped to zero, which — given the publication lag — may understate work still in the pipeline rather than signal exit.
One filer sits well ahead of the field
The leading assignee's 128 records outpace the fifth-place holder's 27, a gap wide enough to indicate a sustained, multi-generation packaging programme rather than a single product cycle.
Research-institute pairs file jointly
The strongest co-assignee pairing links a research institute with a university partner, with academic-industry pairs also appearing among the ten identified co-assignee relationships — a sign that some of the packaging IP originates in joint university-lab programmes rather than solely inside a single company.
US filing dominates, PCT and EPO follow
United States filings (635) dwarf the next-largest receiving offices — WIPO/PCT (109) and Europe (102) — with China (24) and Germany (20) trailing well behind, pointing to the US as the primary jurisdiction of first filing for this technology.
| Assignee | Recent year | YoY |
|---|---|---|
| Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) | 0 | — |
| Akoustis Technologies Corp | 0 | — |
| Raytheon Co | 0 | — |
| Interuniversitair Micro-Electronica Centrum (IMEC) | 0 | — |
| Skyworks Solutions Inc | 0 | — |
| Honeywell International Inc | 0 | — |
| Murata Manufacturing Co., Ltd. | 0 | — |
| Georgia Tech Research Corp | 0 | — |
Where to take this next
The landscape points to where the claim space is dense and where it thins out — the next step is testing a specific claim or filing strategy against it.
Check freedom-to-operate on a specific seal or bonding method
With 42.2% of records held by ten assignees, a targeted FTO search on the exact bonding or sealing method you plan to claim will surface the blocking prior art faster than a broad landscape read.
Run an FTO check in EurekaMap the under-claimed branches against your roadmap
The gate chips above mark thinner filing zones inside a generally dense field; overlaying your own technical roadmap against them shows which are worth a first-filing bet.
Explore white space in EurekaWatch the leading assignee's pipeline, not just its zero-count latest year
Given the roughly 18-month publication lag, a leading filer showing zero in the most recent year may simply have unpublished applications still in process rather than having stopped filing.
Track assignee activity in EurekaCommon questions about this landscape
The ranked list covers 100 assignees, with the leader holding 128 records against 27 for the fifth-place holder and 20 for tenth place. That gap indicates one assignee has built a sustained, multi-generation packaging programme rather than a handful of opportunistic filings. The top five combined hold 31.6% of all 1,027 records in scope, and the top ten hold 42.2%, so a meaningful share of the field still sits outside the leading names in a long tail of single- or few-filing entrants.
Filing peaked at 51 in 2019 and has since eased; the clearest complete-year comparison is 2021 (31) to 2024 (16), a -48% move over that span. Figures for 2025 and 2026 are still incomplete because publication typically lags filing by around 18 months, so it is too early to call the most recent years a continued decline. The honest read is that the technology's core claims are well-established and new filings have slowed from their peak rate.
H01L (semiconductor devices) covers 51.8% of the 1,027 records in scope and is the single largest class, followed by B81C (MEMS manufacturing) at 33.0% and B81B (microstructural MEMS devices) at 31.8%. Records can carry more than one class, so these figures overlap rather than sum to 100%. If your invention touches RF filtering, also check H10W, H10P and H03H, which together mark out the impedance-network and filter side of this dataset.
US6953985B2, assigned to North Star Innovations, claims a method and apparatus for wafer- or array-level MEMS packaging using an array of dielectric lid elements sealed to a MEMS die array, aimed at both hermetic sealing and EM shielding, with an explicit embodiment for RF MEMS switches packaged before singulation. Anyone claiming a similar lidded-array approach to pre-singulation sealing should read its specific claim language closely rather than assume novelty from the general concept of wafer-level sealing. It sits among a small group of highly-cited records that later filers have had to design around or build on.
The core sealing and bonding claims are heavily occupied, with 42.2% of all 1,027 records held by ten assignees, so a direct filing on cavity sealing or lid bonding faces dense prior art. Thinner areas include getter material integration at wafer scale, multi-cavity designs holding different pressures within one package, and hermetic seal verification methods — branches that support the core packaging function but are not the packaging claim itself. These are worth a targeted search before assuming they are open, since thin filing density in a landscape view is a starting signal, not a guarantee of clear space.
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Disclaimer. This page is generated from Patsnap Eureka data drawn from a limited snapshot of global patent and scientific-literature records, and is provided for general information and reference only.
Patent data carries inherent limitations: recent filings (typically the most recent 18–24 months) are under-counted due to standard publication lag; counts may be reported at either a patent-family or a patent-record basis and are not always directly comparable; classification, applicant-name, and citation data may contain errors, duplicates, or omissions; and the underlying search query defines and constrains the scope shown. As a result, the analysis may be incomplete or inaccurate and may not reflect the full technology landscape.
Nothing on this page constitutes an exhaustive prior-art, novelty, freedom-to-operate, or validity search, nor does it constitute legal, financial, investment, or professional advice, and it should not be relied upon as such. Any patent, commercial, or strategic decision should be verified independently and reviewed with qualified patent, legal, and domain professionals. Patsnap makes no warranties, express or implied, as to the accuracy, completeness, or fitness for any particular purpose of the information presented.
Machine translation. Assignee and organisation names originally recorded in Chinese, Japanese or Korean have been rendered into English by an AI translation step so that the tables stay readable. These renderings are best-effort and may not match a company’s registered English name; the original name is what the underlying patent record carries, and it is what any Eureka query launched from this page uses.